https://orcid.org/0000-0001-5630-0529
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Abstract
In this paper, a nine-level inverter topology is proposed with the least number of switches and other components for fault tolerant (FT) operation. The proposed fault tolerant topology requires only one additional switch to execute the fault tolerant operation. The proposed topology also results in reduced total harmonic distortion (THD) as compared with other reported fault tolerant topologies for a 9-level output. A detailed analysis of the topology is presented and the fault tolerant operation is demonstrated under any single, double, triple, and quadruple switch faults using MATLAB/ Simulation and OPALRT hardware in loop (HIL) real time simulator. The proposed concept is validated for single and multiple switch faults and R-L load variation on a low scale laboratory hardware set-up.
ACKNOWLEDGEMENTS
The authors are thankful to All India Council of Technical Education (AICTE) New Delhi for providing National Doctoral Fellowship (NDF) support for this research work.
DISCLOSURE STATEMENT
No potential conflict of interest was reported by the author(s).
Additional information
Notes on contributors
Vinay Kumar
Vinay Kumar obtained his BE in electronics and telecommunication engineering from the Rungta College of Engineering and Technology, Bhilai, Chhattisgarh, India in 2012 and MTech in control systems from BIT Sindari, Jharkhand, India in 2015. He worked as an assistant professor at the Noida Institute of Engineering and Technology, Greater Noida, Uttar Pradesh, India from 2015 to 2018. He is pursuing his PhD in Electrical and Instrumentation Engineering Department of Sant Longowal Institute of Engineering and Technology (SLIET), Longowal, Sangrur, Punjab, India since 2018. His areas of interest are multilevel inverters and fault tolerant operations.
Sanjeev Singh
Sanjeev Singh received his BE in electrical engineering from Awdhesh Pratap Singh University, Rewa, India in 1993, MTech degree from Devi Ahilya Vishwavidya-laya (DAVV), Indore, Madhya Pradesh, India in 1997, and PhD degree from the Indian Institute of Technology Delhi, New Delhi, India in 2011. He was a post- doctoral research fellow at ETS Montreal, Canada in 2016. Presently, he is a professor in the Department of Electrical Engineering, Maulana Azad National Institute of Technology (MANIT), Bhopal, Madhya Pradesh, India. His research interests include power electronics, electrical machines and drives, energy efficiency, and power quality. Email: [email protected]
Shailendra Jain
Shailendra Jain received his BE in electrical engineering from Samrat Ashok Technological Institute (SATI), Vidisha, Madhya Pradesh, India in 1990, ME in power electronics from Shri Govindram Seksaria Institute of Technology and Science (SGSITS), Indore, Madhya Pradesh, India in 1994, PhD degree from the Indian Institute of Technology (IIT), Roorkee, Hardwar, Uttarakhand, India in 2003. He was a post-doctoral research fellow at the University of Western Ontario, London, ON, Canada in 2007. Presently, he is the Director at SLIET Longowal. He has been a recipient of the ‘Career Award for Young Teachers’ from the All India Council for Technical Education (AICTE), New Delhi, India, for the year 2003–2004. He has also authored a book, Modelling and Simulation Using MATLAB-Simulink, published by Wiley in India. His research interests include power electronics and electric drives, power quality improvement, active power filters, high-power-factor converters, and fuel-cell-based distributed generation. Email: [email protected]