Nodal State Comparison-based Dynamic Hold Technique for Low Power OR Gates in Domino Logic

Abstract

This paper presents a novel circuit technique NSCDH, to construct OR gates with 8 inputs up to 128 inputs and single output, which can be cascaded to further stages. It uses stage isolation technique to provide current free nodal state comparison with the ability to hold circuit at an optimal state, thereby resulting in 44.6% lesser power consumption and 16.1% higher noise immunity at 8 inputs as compared to CDDK (2019) and 24.4% lesser power consumption at 128 inputs as compared to CDDK (2019). Circuit simulation is done using HSpice. Standard BSIM4 90 nm PTM file is used to model NMOS and PMOS transistors. Circuit schematic is made using LT Spice. OR gates built using this technique can be used in many applications as multiplexers, read–write data paths, memories, and adders.

KEYWORDS:

• Circuit technique
• Domino logic
• Dynamic logic
• Low power
• Nanoelectronics
• OR gate
• VLSI

DISCLOSURE STATEMENT

No potential conflict of interest was reported by the author(s).

Additional information

Notes on contributors

Manish Tiwari

Manish Tiwari received Bachelor of Engineering degree in electronics and instrumentation in 2008 and MTech from nanotechnology at MANIT, Bhopal, India. He has published research papers in international conferences and journals and has been trained in chip fabrication at IISc Bangalore. Currently, he is pursuing PhD research work in the area of low-power dynamic logic circuits in electronics and communication Department at MANITBhopal. Corresponding author. Email: [email protected]

Vijayshri Chaurasia

Vijayshri Chaurasia received the Bachelor of Engineering degree in electronics and communication in 2005 and MTech in digital communication and PhD in image processing from MANIT, Bhopal, India. She has published 55 research papers in national and international journals and conferences, as author and coauthor. She is a recipient of the MP Young Scientist Award 2012 for electronics, communication, and instrumentation. She is a member of technical bodies such as IEEE, IETE, and ISTE. Currently, she is working as assistant professor, MANIT, Bhopal, India and is involved in research in low-power VLSI and biomedical image processing. Email: [email protected]