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Ferroelectrics Letters Section Volume 40, 2013 - Issue 1-3
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Original Articles

Interface Charge Trap Density of Solution Processed Ferroelectric Gate Thin Film Transistor Using ITO/PZT/Pt Structure

Pham Van Thanh School of Materials Science, Japan Advanced Institute of Science and Technology, Nomi, Ishikawa, 923-1292, Japan; Faculty of Physics, University of Science, Vietnam National University, 334 Nguyen Trai, Thanh Xuan, Hanoi, Vietnam
,
Bui Nguyen Quoc Trinh ERATO, Shimoda Nano-Liquid Process Project, Japan Science and Technology Agency, Nomi, Ishikawa, 923-1211, Japan; Faculty of Engineering Physics and Nanotechnology, University of Engineering and Technology, Vietnam National University, 144 Xuan Thuy, Cau Giay, Hanoi, Vietnam
,
Takaaki Miyasako ERATO, Shimoda Nano-Liquid Process Project, Japan Science and Technology Agency, Nomi, Ishikawa, 923-1211, Japan
,
Phan Trong Tue ERATO, Shimoda Nano-Liquid Process Project, Japan Science and Technology Agency, Nomi, Ishikawa, 923-1211, Japan; Green Devices Research Center, Japan Advanced Institute of Science and Technology, Nomi, Ishikawa, 923-1292, Japan
,
Eisuke Tokumitsu ERATO, Shimoda Nano-Liquid Process Project, Japan Science and Technology Agency, Nomi, Ishikawa, 923-1211, Japan; Green Devices Research Center, Japan Advanced Institute of Science and Technology, Nomi, Ishikawa, 923-1292, Japan
&
Tatsuya Shimoda School of Materials Science, Japan Advanced Institute of Science and Technology, Nomi, Ishikawa, 923-1292, Japan; ERATO, Shimoda Nano-Liquid Process Project, Japan Science and Technology Agency, Nomi, Ishikawa, 923-1211, Japan; Green Devices Research Center, Japan Advanced Institute of Science and Technology, Nomi, Ishikawa, 923-1292, Japan
Pages 17-29 | Accepted 15 Dec 2012, Published online: 13 Aug 2013
 
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Abstract

The conductance method was applied to investigate the interface charge trap density (Dit ) of solution processed ferroelectric gate thin film transistor (FGT) using indium-tin oxide (ITO)/ Pb(Zr,Ti)O3 (PZT)/Pt structure. As a result, a large value of Dit of MFS capacitor, i.e., Pt/PZT/ITO, was estimated to be 1.2 × 1014 eV−1 cm−2. This large Dit means that an interface between the ITO layer and the PZT layer is imperfect and it is one of the main reasons for the poor memory property of this FGT. By using transmission electron microscopy (TEM), this imperfect interface was clearly observed. Thus, it is concluded that improvement of this interface is critical for better memory performance.

Acknowledgments

This work was partially supported by Japan Science and Technology Agency-ERATO-Shimoda Nano Liquid Project. P.V. Thanh gratefully acknowledges financial support by 322 Scholarships (doctoral course) of the Vietnamese Government.

Communicated by Dr. George W. Taylor

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