Control wafers inventory management in the wafer fabrication photolithography area

Abstract

An important variable affecting the production throughput in the wafer fabrication photolithography area is the work-in-process (WIP) level of control wafers. Previous research work has focused on control wafers downgrading problem, and little work has been done for WIP level of control wafers. The objective of this paper is to develop methods for estimating the WIP level of control wafers for each grade, while maintaining the same level of production throughput. Two factors are considered, the re-entrant of control wafers within the same grade and the downgrading of control wafers among different grades. Under pulling control production environment, a multi-loop algorithm is developed for estimating the WIP control wafers for each grade. We conduct some simulation experiments based on a real-world factory production environment to demonstrate the effectiveness of the proposed algorithm. The results show that the algorithm is an efficient tool for estimating the cycle time and WIP level for each grade of control wafers.

Keywords:

• Photolithography area
• Control wafers
• Inventory
• Multi-loop
• Re-entrant
• Downgrade

Acknowledgement

This research is supported in part by Grant NSC91-2416-H-009-014.

Dr. Shu-Hsing Chung is Professor of the Department of Industrial Engineering and Management, National Chiao-Tung University, Taiwan, ROC. She received her PhD degree in industrial engineering from Texas A&M University, College Station, TX, USA. Her research interests include production planning, scheduling, and cycle time estimation. She has published and presented research papers in the areas of production planning and scheduling for IC manufacturing.

Dr. Wen Lea Pearn is Professor of the Department of Industrial Engineering and Management, National Chiao-Tung University, Taiwan, ROC. He received his PhD degree in operations research from the University of Maryland, College Park, MD, USA. He worked for AT&T Bell Laboratories Switch Network Control and Process Quality Centers. He has published numerous papers in the areas of network optimization, machine scheduling, and process capability analysis.

Dr. He-Yau Kang is Associate Professor of the Department of Industrial Engineering and Management, National Chin-Yi Institute of Technology, Taiwan, ROC. He received his PhD degree in industrial engineering and management from National Chiao-Tung University. His research interests include production planning, scheduling, and performance evaluation.