Carbon Nanotube Interconnects − A Promising Solution for VLSI Circuits

ABSTRACT

In nanoscale regime, the performance of traditional copper interconnects degrades substantially in terms of latency, power dissipation and induced crosstalk noise. This is due to miniaturization of electronic devices and many-fold enhancement of interconnect lengths in very large-scale integrated (VLSI) circuits. However, carbon nanotubes (CNTs) due to their unique physical properties such as high thermal conductivity, current carrying capability and mechanical strength have drawn the attention of researchers in recent times. The present paper provides comprehensive investigations in the various CNT structures for on-chip VLSI interconnect applications. Different configurations of CNT structures are studied namely single-wall CNT (SWCNT), multiwall CNT (MWCNT) and mixed-wall CNT bundle (MCB). The performance of CNT interconnects is analyzed using driver-interconnect-load system. It is investigated that the reduction in propagation delay in MCB interconnect is nearly 69%, 60%, 40% and 22% as compared to copper, SWCNT bundle, MWCNT and MWCNT bundle interconnect structures, respectively. This analysis considers an interconnect length variation from 500 to 2500 µm for 32-nm technology node. For the same dimensions the overall reduction in power dissipation in MCB interconnect is nearly 60%, 49%, 45% and 36% as compared to copper, SWCNT, MWCNT and MWCNT bundle interconnects, respectively. Furthermore, the effect of crosstalk on the interconnect structures has been examined. It is investigated that MCB has least crosstalk induced delay than all the other interconnect structures. Consequently, it is envisaged that MCB outperforms copper, SWCNT, MWCNT and MWCNT bundle interconnects and are best suited for future VLSI interconnects.

KEYWORDS:

• Carbon nanotube (CNT)
• Copper
• Crosstalk
• Delay
• MCB
• MWCNT
• SWCNT
• VLSI interconnects

DISCLOSURE STATEMENT

No potential conflict of interest was reported by the authors.

Additional information

Notes on contributors

Mekala Girish Kumar

Mekala Girish Kumar received BTech degree in electronics and communication engineering from Saispurthi Institute of Technlogy, Sathupally, in 2008 and MTech degree in VLSI Design Automation and Techniques from National Institute of Technology, Hamirpur, India, in 2011. He is currently pursuing his PhD degree from National Institute of Technology, Hamirpur, India. His current research interests include investigation and modeling of CNT and GNR interconnects for deep sub-micron technologies.

E-mail: [email protected]; [email protected]

Yash Agrawal

Yash Agrawal received his BE degree in electronics and communication engineering from the Kavikulguru Institute of Technology and Science, Ramtek, Maharashtra, in 2009 and MTech degree in VLSI design automation and techniques from NIT, Hamirpur, India, in 2012. He is currently working towards his PhD degree from NIT, Hamirpur, India. His current research interests include design techniques and modeling of high speed on-chip VLSI interconnects. He achieved university rank during his bachelor's degree. He achieved the third place in all India Mentor Graphics design contest held at Bangalore, India, in 2011. He is a student member of IEEE.

E-mail: [email protected]

Rajeevan Chandel

Rajeevan Chandel received her BE degree in electronics and communication engineering from Thapar University, Patiala, India, in 1990. She is a double gold medalist of Himachal Pradesh University, Shimla, India, in Pre-University and Pre-Engineering in 1985 and 1986, respectively. She received her MTech degree in Integrated Electronics and Circuits from Indian Institute of Technology (IIT), Delhi, India, in 1997. She was awarded PhD degree from IIT Roorkee, India, under QIP scheme of Government of India in 2005. She joined the Department of Electronics and Communication Engineering, NIT, Hamirpur, India, as a lecturer in 1990, where she is presently working as a professor and has been the head of the department twice. She has five MHRD, MCIT sponsored projects to her credit from the Government of India. She has published over 50 research papers in international and national journals of repute and over 75 in conferences. Her research interest includes electronics circuit modeling and low-power VLSI design. She is a Fellow of IETE(I), Life Member of ISTE(I), ISSS and Member of IEEE.

E-mail: [email protected]