A Ferroelectric Capacitor Mathematical Model for Spice Simulation

Abstract

A behavioral ferroelectric capacitor model based on Q-V expression with model parameters extracted from experimental hysteresis loops is proposed. A compact equivalent circuit of this model is described for spice simulation of nonvolatile memories. Excellent agreement was achieved between our measurements and simulation results. The runtime for simulation of a hysteresis loop with 10,000 points is 1.55 seconds, which is similar to 1.15 seconds for a normal capacitor.

Keywords:

• ferroelectric capacitor
• Q-V expression
• hysteresis loop
• equivalent circuit