Investigation of tunneling layer and inter-gate-dielectric engineered TaN floating gate memory

ABSTRACT

Metal as floating gate (FG) in combination with high-k dielectrics has been seen as a possible solution to continue the scaling of NAND flash technology node beyond 2X nm. In this work, metal FG memory device with high-k engineered Inter-Gate-Dielectric (IGD) and/or tunneling layer (TL) was detailed investigated. It presents improved performance with lower operation voltage as well as faster speed, compared to control samples. Furthermore, improvement of long-term data retention is observed for the high-k engineered devices, proving that the introduction of engineered IGD and/or TL is a promising solution for further performance improvement of full metal FG memory device.

Keywords:

• Metal floating gate memory
• high-k
• engineered barrier

Funding

This work was supported by the National Natural Science Foundation of China (Grant No. 61474137, No. 61306107, No. 61404168, No. 61404160), China Postdoctoral Science Foundation funded project (No.2014M550866), and the Scientific Research Foundation of CUIT (KYTZ201318, J201404).