Real-time hardware implementation of a speed FSBMA used in H.264/AVC

Abstract

Nowadays, H.264/AVC reaches very high resolutions, flexible depending on the application, which particularly leads to a very large amount of data compression. The motion estimation defines the most-complex process and the most interesting at the same time; its complexity appears with a consumption of more than 60% of total encoding time which make it difficult to achieve real-time encoding required in many video applications, but the interesting part is the flexibility to make its implementation variant according to the application. For this purpose, the following paper presents a speed real-time hardware implementation of integer motion estimation used in H.264/AVC, the method is based on the full-search block-matching algorithm. The proposed architecture calculates best motion vector using a parallel process. It is composed of three processor modules and a comparator three values. Implementation results based on Field Programmable Gate Array devices uses Xilinx Virtex7 XC7VX550T show performance characteristics like low latency, high processing speed reaching 473 MHz of frequency. The processing capacity is up to 1080HD video streams with a search range of 48 × 48.

Keywords:

• Full-search block-matching
• H.264/AVC
• motion estimation
• video compression
• hardware implementation