Design considerations and optimisation of clock circuit for ultra-low power sub-threshold applications

ABSTRACT

Clock system plays a vital role in governing the reliability, power consumption and performance of synchronous system. In today’s era of portable electronics, power consumption has emerged as a forefront design metrics. Sub-threshold operation of devices is an excellent option to have an ultra-low power system. However, degraded performance and exacerbated variability are the major concerns of the sub-threshold circuits. Furthermore, as contradictory to the conventional super threshold circuits, the device resistance for the sub-threshold circuits is quite high compared to the interconnect resistance. This paper therefore, explores the design constraints for sub-threshold clock system. It further explores the suitability of buffered and un-buffered clock system in deep sub-threshold regime. The impact of supply voltage scaling and 3σ/µ variability for clock system is investigated in this work. An attempt to improve the slew of the clock system with un-buffered tree is made by redesigning the tapered H tree which exhibits better slew and robustness in sub-threshold regime.

KEYWORDS:

• sub-threshold
• voltage controlled oscillator (VCO)
• current starved VCO (CSVCO)
• PVT (processvoltage and temperature) variations
• Monte Carlo simulations