Remora Optimized Dynamic Neural Network to Design Low-Power CNTFET Logic Gate Realization with Multiple-Valued Circuits

Abstract

The emerging trend of new digital technology leads to the requirement of small, faster, and low-power consumed processors. The advanced 5 G technology forces the usage of enhanced battery life, maximized spectral efficiency, etc., these can be achieved by the inclusion of a Carbon nanotube field-effect transistor (CNTFET). The proposed multiple-valued logic circuits (MVL) are designed using some of the unique features of the CNTFET such as high transconductance, setting of desired threshold voltage, and similar mobility of P and N-type devices. For designing low-power and optimized logic gate realization we have utilized the inherent binary gates along with the CMOS architecture. Further, an artificial intelligence approach known as Dynamic Neural Network (DNN) is adopted for the realization of logic gates in the MVL with the employment of lesser MVL operators. To enhance the parameter utilization of DNN with the help of tuning, we exploited the Remora Optimization algorithm (ROA). The results are obtained by conducting experiments on HFSS software. This approach is designed to reduce the static power dissipation, the number of logic gates, and network propagation delay. Compared to the existing methods, the proposed technique outlined a standard voltage of 32 nm that considers 0.9 V supply voltage. The result of our proposed method can be deviated by only 25% and thus outperforms all the other approaches. The standby power consumption of proposed approach is 2.12 W

Keywords:

• logic gates
• Multiple-valued logic gates
• CMOS
• CNTFET
• low-power consumption
• and optimized area

DISCLOSURE STATEMENT

The authors declare that they have no conflict of interest.

HUMAN AND ANIMAL RIGHTS

This article does not contain any studies with human or animal subjects performed by any of the authors.

INFORMED CONSENT

Informed consent does not apply as this was a retrospective review with no identifying patient information.

DATA AVAILABILITY STATETMENT

Data sharing is not applicable to this article as no new data were created or analyzed in this study.

Additional information

Notes on contributors

Sriram Sandhya Rani

Sriram Sandhya Rani received Ph.D degree from Koneru Lakshmaiah Education Foundation (KL deemed to be University), Guntur, Andhra Pradesh, India in the year 2020. She is currently working as a Professor with the Department of ECE, Jayamukhi Institute of Technological Sciences, Warangal, Telangana, India. Her research interests include the design of Antennas and Microwave circuits, Wireless Communication, VLSI and Signal Processing.

Hameed Pasha Mohammad

Hameed Pasha Mohammad received Ph.D degree from Visveswaraya Technological University (VTU Belagavi), India in the year 2023. He is presently working as Associate Professor and Head of the ECE Department at Jayamukhi Institute of Technological Sciences, Warangal Telangana state. His area of Interest is VLSI Technology and Design, Internet of Things, Artificial Intelligence and Machine Learning.

Sheik Masthan

Sheik Masthan received his Ph.D. degree in electronics and communication Engineering from the University of Sri Satya Sai University of Technology & Medical Sciences, Sehore, Madyapradesh in the year 2021. Presently working as an Associate Professor in Jayamukhi Institute of technological Sciences, Warangal, Telanagana. His research interests are adaptive signal processing and VLSI design.