Capacitance Parameter Extraction and Modeling for Amorphous Silicon Thin-Film Transistors

Abstract

This paper presents modeling and parameter extraction of the capacitance characteristics of the inverted-staggered a-Si:H TFT in both the depletion and inversion regions of operation. The need for a model of the capacitance with variable gate-source or gate-drain bias is imperative for a robust circuit design. However, the previous model parameter expression is applied to the staggered a-Si:H TFT. In this paper, we investigated the capacitance characteristics and modeling using the new extracted method for the inverted staggered structure. The accuracy of the simulated curves using parameters extracted with the new procedure is verified with measured and calculated data.

Keywords:

• Thin Film Transistor
• a-Si:H transistor model
• Kick-back Effect
• Parameter Extraction
• Voltage-Controlled Capacitance