Charge transfer enabled by the p-doping of WSe₂ for 2D material-based printable electronics

Abstract

Here, we report the fabrication of high-performance printable WSe₂ transistors via the doping of p-type FeCl₃ molecules (hole mobility: ∼1.5 cm² V⁻¹ s⁻¹; on/off ratio: ∼10⁶). A complementary inverter is demonstrated with p-WSe₂ and n-MoS₂ transistors, which highlights its potential for application in future two-dimensional material-based printable electronics.

KEYWORDS:

• 2D materials
• WSe₂
• molecules doping
• printable electronics
• CMOS inverter

1. Introduction

The past few decades have witnessed the rapid development of inks based on two-dimensional (2D) materials owing to their potential for diverse industrial applications, including energy harvesting and conversion, sensors, photovoltaics, and flexible electronics [1]. Among them, transition metal dichalcogenides (TMDs) are a promising and unique class of materials, and have been used as building blocks in fundamental printable (opto)electronic applications, such as thin-film transistors (TFTs), superconductors, supercapacitors, detectors, and logic circuits [2,3], due to their versatility from insulators, semiconductors, semimetals, to metals [4].

Recent research has particularly focused on 2D complementary metal–oxide semiconductor (CMOS) technology [5] since it forms the backbone of integrated circuits. However, most solution-processed CMOS circuits based on 2D TMD inks were fabricated by integrating n-type MoS₂ with p-type carbon nanotubes (CNTs) or organic semiconductors [6-8], but rarely were they fabricated with p-type 2D TMD semiconductors [5]. This was mainly due to the inferior electrical performance of solution-processed p-type TMD transistors compared to that of n-type ones, resulting in a considerable mismatch in the device performance when applying CMOS technology. For instance, a solution-processed p-type transistor fabricated with undoped 2D WS₂ semiconductors exhibited a mobility of 0.22 cm² V⁻¹ s⁻¹，and an on/off ratio of approximately 10² [9]. In contrast, solution-processed MoS₂ TFTs were reported to exhibit a mobility of approximately 10 cm² V⁻¹ s⁻¹, with a high on/off ratio of approximately 10⁶ [3,8,10], while In₂Se₃ TFTs exhibited mobility of 0.4 cm² V⁻¹ s⁻¹ and an on/off ratio of approximately 10³ [11]. The low hole mobility of solution-processed p-type 2D TMD TFTs consisting of aligned nanoflakes can primarily be attributed to the high contact resistance and inefficient carrier transport in the channel [12,13].

Fermi-level pinning at metal contacts to create a large hole Schottky barrier height (SBH) can contribute to high contact resistance. Although metals of different work functions have been used, the SBH was still over 1 eV for hole injection [14]. Further, obtaining an ultra-clean surface and high-quality 2D semiconductors by liquid-phase exfoliation compared to mechanical exfoliation can be challenging. Hence, the existence of surface impurities and intrinsic defects originating from the 2D semiconductor could induce Fermi-level pinning [15]. On the other hand, the resistance among nanoflakes could also contribute to a high channel resistance, hindering charge transport [13]. The interfacial resistance in 2D semiconductor films could reach 100 GΩ, significantly higher than the interfacial resistance (1-5 MΩ) [16]. To overcome the aforementioned limitations, molecular doping has been considered an effective approach for improving the electrical properties of solution-processed TFTs, and this was proven for mechanically exfoliated single-flake transistors. For instance, Kim et.al demonstrated the depinning of the Fermi level via molecular doping onto a MoTe₂ channel to significantly lower the SBH and reduce the contact resistance [17]. Lee et.al revealed that the carrier density and conductivity of WSe₂ can be more effectively modulated by using an appropriate molecular dopant, and that the amount of charge transfer between WSe₂ and the dopants is determined by both, the doping density and the contribution of each dopant ion toward Coulomb scattering [18]. In addition, molecular doping has been shown to be advantageous in terms of being a relatively non-destructive process and being applicable with a diverse range of potential dopants [19].

Hence, in this study, we selected iron (III) trichloride (FeCl₃), an oxidative dopant that has been widely used as a p dopant in organic semiconductors [20,21], as a representative dopant to achieve the desired device performance for solution-processed p-type WSe₂ TFTs. The doped WSe₂ TFTs exhibited typical p-type behavior compared to the ambipolar behavior for pristine devices. We systematically investigated the influence of the FeCl₃ concentration on the solution-processed WSe₂ TFTs to modulate the contact resistance, carrier concentration, and trap density. We also developed a simple photolithography process with drop-casting to pattern the semiconducting films, which enabled us to integrate n-type and p-type TMD TFTs for fabricating printable CMOS inverters.

2. Results and discussion

WSe₂ nanoflakes were prepared as p-type transistors through an electrochemical intercalation approach, according to the literature [3]. Briefly, tetraethylammonium bromide (THAB) dissolved in acetonitrile was used as the electrolyte. A copper plate with an attached WSe₂ crystal was used as the cathode, and a graphite rod was used as the opposite anode. Subsequently, a voltage of 15 V was applied for 1 h to intercalate the WSe₂ crystal. The intercalated WSe₂ crystal was then sonicated in dimethylformamide (DMF)/polyvinylpyrrolidone (PVP) solution for 30 min. Finally, the obtained WSe₂ nanoflakes were washed and dispersed in isopropanol (IPA). The ultraviolet (UV)-visible spectrum in Figure 1(a) shows two feature peaks at A (761 nm) and B (590 nm), which are mainly attributed to the splitting of the valence band due to spin–orbit coupling [22]. The origination of the other two peaks at A′ (518 nm) and B′ (436 nm) is believed to be the perturbation to the d electron band by the Se p orbitals, which causes the splitting of the ground and excited states of A and B transitions, separately [23]. The Raman spectrum in Figure 1(b) shows characteristic E_2g¹ (246 cm⁻¹) and A_1g (254 cm⁻¹) peaks, corresponding to transition metal and chalcogen atoms’ in-place displacement and out-of-plane vibration of chalcogen atoms, respectively [24]. The WSe₂ nanoflakes also exhibit a PL peak at 1.64 eV (Figure S2). The atomic force microscopy (AFM) image in Figure 1(c) shows that the exfoliated WSe₂ nanoflakes have a lateral dimension of 1–2 µm and a thickness of ∼3 nm. The high-resolution transmission electron microscopy (HRTEM) image reveals that the exfoliated WSe₂ nanoflakes have a high crystallinity (Figure 1(d)). The electron hexagonal diffraction pattern shows that the interlayer distance of the (100) plane is 0.28 nm, in agreement with the reported distance in WSe₂ [25]. We also prepared MoS₂ inks by the same electrochemical intercalation approach and similarly characterized as the prepared MoS₂ nanoflakes. The results are shown in Figure S1-3. The findings confirm the successful preparation of semiconducting 2H-phase WSe₂ and MoS₂ nanoflakes.

Figure 1. (a) UV-visible spectrum of the as-prepared WSe₂ solution. The inset shows the photograph of each dispersion in isopropanol. (b) Raman spectra of WSe₂. The inset shows the atomic displacement of the E_2g¹ and A_1g Raman-active modes. (c) AFM image of the exfoliated WSe₂ nanoflakes and the corresponding height profile (scale bar: 500 nm). (d) High-resolution TEM image of the exfoliated WSe₂ nanoflakes. The inset shows the selected-area electron diffraction image (scale bar: 2 nm).

Different methods have been explored to fabricate patterned semiconductor thin films, such as spin coating [3], inkjet or spray printing [8], and layer-by-layer (LbL) assembly [10]. However, spin coating typically requires an additional reactive ion etching (RIE) process to pattern the channel, while for inkjet printing, the surface tension and viscosity of the ink should be optimized well. To simplify the fabrication process, in this study, we patterned the solution-processed TMD thin films by photolithography and drop-casting (Figure 2(a)). Firstly, a photoresist (PR) was patterned via photolithography to define the desired area for the semiconductor film. In this study, the SU-8 (Kayaku Advanced Materials, Inc.) PR was selected because it can survive from the immersion in IPA after crosslinking with UV exposure. Subsequently, 2D inks were drop-casted on the patterned PR and dried slowly. The substrate was covered with a Petri dish. In this way, the IPA vapor could retard the solvent evaporation rate. The liquid WSe₂ solution on the substrate will become thinner slowly, and the concentration of the solution will increase gradually. Thus, the WSe₂ nanoflakes tend to vertically stack together to form a high-quality and fine alignment of WSe₂ thin film. We then stripped off the PR, leaving only the patterned semiconductor thin film on the substrate. To complete the transistor fabrication, the substrate with the semiconductor thin film was annealed on a hotplate in a nitrogen-filled glovebox at 200 °C for one hour to evaporate the IPA solvent. Finally, the electrodes were thermally evaporated and patterned via photolithography. Figure 2(b) shows the WSe₂ TFT with a patterned and compact semiconductor thin film. The edge between the semiconductor thin film and substrate is distinguishable. The cross-sectional TEM image (Figure 2(c)) shows that the film has multiple overlapping flakes with a clearly distinguishable interface between the flakes. The layered structures are parallel to the surface and have a thickness of ∼10 nm. In the transistor fabrication process, most processes were conducted in ambient conditions, except for the annealing step in the glove box and electrode deposition in a high-vacuum chamber. Thus, our method is low-cost and easy and could be applicable for large-scale assembly and the fabrication of flexible or wearable complex circuits with 2D functional materials.

Figure 2. (a) Schematic of transistor fabrication by drop-casting with the 2D ink. (b) Optical micrograph of the as-fabricated WSe₂ transistor (scale bar: 100 µm). (c) Cross-sectional TEM image of the WSe₂ thin film on the Si/SiO₂ substrate (scale bar: 20 nm).

Furthermore, we investigated the electrical properties of the as-prepared WSe₂ TFTs. The I_DS–V_GS transfer curve (Figure 3(a)) reveals an ambipolar behavior for the pristine WSe₂ TFT, with hole and electron conduction occurring below −15 V and above 40 V, respectively, implying a Fermi-level pinning effect that can be modulated by molecular doping [17]. Consequently, the pristine WSe₂ TFT exhibits a low on/off ratio of ∼5 × 10³. The field-effect channel mobility (µ_FE) was estimated using the following equation: ${\mu }_{FE}=\frac{\mathrm{\partial }{I}_{DS}}{\mathrm{\partial }{V}_{GS}}\frac{L}{W}\frac{1}{C_i{V}_{DS}}$where L is the channel length, W is the channel width, C_i is the gate dielectric capacitance per unit area, and V_DS is the applied source–drain voltage. The pristine WSe₂ TFT had a low hole µ_FE of 1.5 × 10⁻³ cm² V⁻¹ s⁻¹.

Figure 3. (a) I_DS–V_GS transfer curves at V_DS = −1 V for the pristine and FeCl₃-doped WSe₂ (60 µg/mL) TFTs on a SiO₂/Si substrate with a 100 nm-thick SiO₂ layer. V_DS is −1 V. The width and length of the channel are 725 and 50 µm, respectively. (b) Output curve of the corresponding FeCl₃-doped WSe₂ TFT. (c) UPS spectra showing the secondary electron cut-off and (d) valence band of pristine and FeCl₃-doped WSe₂ thin films (60 µg/mL). (e) Schematic energy diagram of the Ni/Au and WSe₂ contacts before and after doping. (f) Schematic energy diagram at the interface between the nanoflakes in the channel with a bias voltage applied after doping.

FeCl₃ was applied as a dopant to modulate the electronic properties and control the carrier concentration. In this procedure, FeCl₃ powders were dissolved in 1,2-dichlorobenzene solvent to obtain solutions of different concentrations. The pristine device was then immersed in the FeCl₃ solutions and annealed at 80°C for 30 min in ambient conditions. After doping with FeCl₃, the I_DS–V_GS transfer curve showed clear p-type characteristics with an increased on-current at V_GS = −50 V and a positive shift in the threshold voltage (V_th), representing a p-doing effect. The resulting WSe₂ TFT showed a significantly improved µ_FE up to 1.0 cm² V⁻¹ s⁻¹, which is approximately three orders of magnitude higher than the pristine WSe₂ TFT. Note that our FeCl₃-treated WSe₂ TFT maintained a low off-current below 1 × 10⁻¹¹ A and showed a high on/off ratio of ∼3.0 × 10⁶, unlike reported results where some doping treatments had negatively affected the on/off ratio [26,27]. The output curve after FeCl₃ doping also indicated that the WSe₂ TFT had a relatively low contact resistance (Figure 3(b)). Thus, our doping method achieves better device mobility and on/off ratio than the pristine WSe₂ TFT and other reported solution-processed p-type 2D TMD TFTs [9,13]. Our obtained values are comparable to those of solution-processed n-type 2D TMD transistors [3,8,10]. A detailed comparison is provided in Table S1.

The doped hole carrier density can be regulated according to the FeCl₃ concentration, as evidenced by the I_DS–V_GS transfer curve (Figure S4a). With increasing FeCl₃ concentration, there is a gradual positive shift in V_th from −35 V for the pristine device to −10 V after treatment with a 120 µg/mL FeCl₃ solution. Increasing the FeCl₃ solution concentration to 120 µg/mL results in a hole µ_FE of ∼1.5 cm² V⁻¹ s⁻¹ and a high on/off ratio of 1.4 × 10⁶ (Figure S4b). However, using a higher doping concentration can introduce excess charges in the WSe₂ thin film, ultimately increasing the off-current. Consequently, a larger positive bias is needed to f deplete the excess charges and turn off the device fully. The hole density (n__hole) of the FeCl₃-doped WSe₂ TFT was calculated using the equation n__hole= (I_DSL)/(qWV_DSµ), where q is the electron charge [26,28]. The calculated n__hole as a function of the FeCl₃ solution concentration is plotted in Figure S5. The n__hole at V_GS = 0 V increases from 8.4 × 10¹¹ to 5.1 × 10¹² cm⁻² with an increase in the FeCl₃ solution concentration from 1.2–120 µg/mL. The hole density of the undoped WSe₂ film is estimated to be approximately 5 × 10¹¹ cm⁻². The amount of generated carrier hole density by doping is comparable to previously reported data (3.6 × 10¹² cm⁻² for F₄-TCNQ-doped WSe₂ and 4.5 × 10¹² cm⁻² for Mo(tfd-COCF₃)₃-doped WSe₂) [18].

Ultraviolet photoemission spectroscopy (UPS) is a direct measurement method to demonstrate the doping effect and work function change [29]. The secondary electron cut-off spectrum (Figure 3(c)) shows a downward shift in the Fermi level from −4.11 eV to −4.55 eV after the FeCl₃ treatment of the WSe₂ thin film. The distance between the valence-band maximum (E_VBM) to the Fermi level (E_F) also shifts from 1.47 eV to 0.98 eV (Figure 3(d)). The downshift of E_F to E_VBM indicates the occurrence of considerable electron transfer from the WSe₂ to FeCl₃ molecules, i.e. the p-type doping effect in the WSe₂ film, which may be attributed to the low electron affinity (EA) of the oxidizing agent, FeCl₃ (EA = −4.65 eV) [21,30].

The downshift in E_F for the FeCl₃-doped WSe₂ TFT would also lower the SBH and narrow the depletion region, facilitating easier hole injection (Figure 3(e)) [31]. In contrast, for the pristine WSe₂ TFT, carrier injection is dominated by thermionic emission because of the large SBH and thick depletion layer due to the Fermi-level pinning effect. The contact resistance (R_c) was extracted by the Y-function method [32]. R_c considerably decreased to 3.1 × 10³ kΩ µm after FeCl₃ doping, which is approximately three orders of magnitude lower than that of the pristine WSe₂ TFT (2.3 × 10⁶ kΩ µm). We propose that the high on/off ratio observed after FeCl₃ p-doping can be attributed to the reduction in the SBH for hole injection with moderate doping concentration, resulting in a decrease in contact resistance. First, the effectively reduced hole SBH through moderate p-doping facilitates hole injection, increasing the effective SBH for electrons. Second, the moderate p-doping can enhance the conductivity of the channel and reduce the electron concentration in the 2D semiconductor layer. Meanwhile, moderate doping allows the applied gate voltage to completely deplete the introduced free charges in the device. These effects are advantageous for achieving a high on-state current and a low off-current.

On the other hand, the subthreshold swing (SS) decreased from 4.0 V/dec for the pristine WSe₂ TFT to 2.6 V/dec after FeCl₃ treatment. Accordingly, the total trap density (N_trap) values were estimated to be 1.52 × 10¹³ cm⁻² eV⁻¹ and 9.8 × 10¹² cm⁻² eV⁻¹ for the pristine and FeCl₃-doped WSe₂ TFTs, respectively [33]. Trap states are typically generated at the gate insulator/semiconductor interface and interflake interfaces because of the bubbles or wrinkles. They can induce scattering of the charge carriers, thereby hindering carrier transport [34]. Our results indicate that the generated free carriers by p-doping can fill the trap states and effectively screen the trapped charges (Figure 3(f)), leading to increased carrier mobility. Based on the theoretical model of charge transport on grain boundaries [35,36], the effective height of the potential barrier on the forward bias side is E_B-qV_B, which plays a significant role in charge transport, and that on the reverse bias is E_B+ qV_B, where E_B is the height of potential barrier at grain boundaries, and V_B is the voltage drop across grain boundaries. The doping effect can modulate the effective height of the potential barrier by influencing the total carrier density, the resistance from the grain boundaries and the crystallite, and so on [35]. To obtain a precise and quantitative analysis of the dependence of the height of the barrier on the doping, a proper theoretical model and additional experiments are required for 2D thin film systems.

Based on the aforementioned lift-off-based patterning method, we fabricated a CMOS inverter composed of solution-processed p-WSe₂ and n-MoS₂ TFTs (Figure 4(a,b)). The WSe₂ thin film was first deposited on a 100 nm-thick SiO₂/Si substrate, following which the MoS₂ thin film was deposited. Our n-MoS₂ TFTs exhibited a mobility of ∼5 cm² V⁻¹ s⁻¹ after treatment with bis(trifluoromethane)sulfonimide (TFSI) (Figure S6), similar to the previous report [3,37]. The drain currents of the p-WSe₂ and n-MoS₂ TFTs were adjusted to the same level by controlling the channel width and doping concentration. The CMOS inverters exhibited an ideal steep switching behavior in the voltage transfer characteristic curve (Figure 4(c)). A voltage gain of 3.5 was achieved under a driving voltage (V_DD) of 8 V (Figure 4(d)). The gain was comparable to previously reported study on a printed CNT/MoS₂ CMOS inverter (Table S2) [7,8]. We expect to attain higher gains through further optimization of the subthreshold slope by increasing the gate insulator capacitance per unit area [38].

Figure 4. Solution-processed complementary metal-oxide-semiconductor (CMOS) inverter. (a) Circuit diagram of the CMOS inverter. (b) Schematic of a CMOS inverter with p-WSe₂ and n-MoS₂ channels. (c) Voltage transfer characteristics of the CMOS inverter as a function of the input voltage with different V_DD values from 1 to 8 V. The FeCl₃-doping concentration for p-WSe₂ is 60 µg/mL. (d) Corresponding gains of the inverter from c at V_DD = 8 V.

3. Conclusion

Our work demonstrates a general molecular doping approach to fabricate high-performance solution-processed p-channel transistors using WSe₂ semiconductors. We also present a simple photolithography process involving drop-casting to obtain a patterned semiconducting film. Thus, we successfully demonstrate the fabrication of a CMOS inverter integrated with p-type WSe₂ and n-type MoS₂ semiconductors. Most importantly, this study provides a series of robust routes to use 2D material inks and integrate multiple semiconductors to realize printable electronic devices. Therefore, our work paved the way for future ultrathin, flexible, and wearable electronic and optoelectronic applications.

Disclosure statement

No potential conflict of interest was reported by the author(s).

Additional information

Funding

This study was supported by the Ministry of Science and ICT of the government of South Korea through the National Research Foundation, funded by the Korean government (2020M3D1A1110548 and 2020M3D1A1110549). This research was also supported by Samsung Display Corporation.

Notes on contributors

Taoyu Zou

Taoyu Zou received his M.S. degree from the Department of Physics and Astronomy of Yunnan University, China, in 2016. He is currently a Ph.D. candidate at the Department of Chemical Engineering of the Pohang University of Science and Technology (POSTECH) under the supervision of Prof. Yong-Young Noh. His current research interests include solution-processed 2D materials for thin-film transistors and circuits.

Haksoon Jung

Haksoon Jung is currently a Ph.D. student in the Department of Chemical Engineering at Pohang University of Science and Technology (POSTECH) under the supervision of Prof. Yong-Young Noh. He received his B.S. degree from the Department of Energy and Materials Engineering of Dongguk University, Korea, in 2019. His research interests include emerging semiconductor materials and devices.

Ao Liu

Ao Liu is a postdoc at the Department of Chemical Engineering of Pohang University of Science and Technology (POSTECH). He received his Ph.D. degree from the Department of Chemical Engineering at Pohang University of Science and Technology (POSTECH) in 2022. His research interests include the development of solution-processed metal oxide/organic materials and their applications in transistors and circuits.

Soonhyo Kim

Soonhyo Kim received his B.S. degree in Chemical Engineering from the Pohang University of Science and Technology (POSTECH) in 2020. He is currently a Ph.D. candidate in the Department of Chemical Engineering at POSTECH under the supervision of Prof. Yong-Young Noh. His research interests include the development of semiconductors for transistors based on computational and experimental methods.

Youjin Reo

Youjin Reo received her B.S. degree in Chemical Engineering from the Pohang University of Science and Technology (POSTECH) in 2020. She is currently a Ph.D. candidate in the Department of Chemical Engineering at POSTECH under the supervision of Prof. Yong-Young Noh. Her research interests include the development of perovskite-based semiconductors through solution-process and thermal deposition, as well as their applications in transistors and circuits.

Taesu Choi

Taesu Choi received his B.S. degree in Chemical Engineering from the Pohang University of Science and Technology (POSTECH) in 2020. He is currently a Ph.D. candidate in the Department of Chemical Engineering at POSTECH under the supervision of Prof. Yong-Young Noh. His research interests include oxide semiconductors by thermal deposition.

Yong-Young Noh

Yong-Young Noh is the Chair Professor of the Department of Chemical Engineering of Pohang University of Science and Technology (POSTECH). He received his Ph.D. degree in 2005 from GIST and then worked at the Cavendish Laboratory in Cambridge, UK, as a postdoctoral associate. Afterward, he worked at ETRI as a senior researcher, as assistant professor at Hanbat National University, and as associate professor at Dongguk University. His research interest is in the field of developing printable semiconductors including 2D materials, organic, carbon nanotubes, perovskite, metal halide and metal oxide for field-effect transistors, photodetectors, and light-emitting diodes.