A novel LTPO AMOLED pixel circuit and driving scheme for variable refresh rate

Abstract

This paper proposes a novel pixel circuit and driving scheme that adopts low-temperature polycrystalline silicon and oxide thin-film transistors (LTPO TFTs) for mobile devices using active-matrix organic light-emitting diode (AMOLED) displays. The proposed pixel circuit and driving scheme provide uniform luminance and render flicker invisible at variable refresh rates (VRRs) from 1 to 120 Hz. Using the proposed pixel circuit with extended compensation time (t_COMP) improves the luminance uniformity at a high-frame rate. The proposed driving scheme applies a voltage to the driving TFTs (D-TFTs) higher than the programmed data voltage during the skip frame. This reduces the flicker caused by the hysteresis of D-TFTs during low-frame rate driving. A 6.0-inch quad high-definition (QHD) LTPO-based AMOLED display was fabricated using the new pixel circuit and driving scheme. Experimental results of the proposed pixel circuit show that the standard deviation of luminance was reduced from 0.056 to 0.008 by extending t_COMP from 2 to 8 µs. The flicker level was −51 dB, so there was no visual artifact during 1 Hz driving. A flicker-free LTPO-based AMOLED display with low power consumption is possible; driving can proceed in 1–120 Hz range.

KEYWORDS:

• Low-temperature polycrystalline and oxide (LTPO)
• variable refresh rate (VRR)
• flicker
• hysteresis

1. Introduction

In recent years, display backplane technology has been developed from hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) to low-temperature polycrystalline silicon (LTPS) TFTs and then to low-temperature polycrystalline silicon and oxide (LTPO) TFTs [1–4]. Specifically, LTPO TFTs constitute the next-generation backplane technology for smartphones and smartwatches using active-matrix organic light-emitting diode (AMOLED) display because such devices must be driven at high- and low-frame rates (i.e. variable refresh rate [VRR]) in a power-efficient manner [17,27]. A VRR driving is required for the following reasons: Fast-motion image scenarios, such as gaming and display scrolling, demand a high-frame rate of up to 120 Hz, whereas a low-frame rate down to 1 Hz is appropriate in low-power standby scenarios, such as the always-on display (AOD) and text mode. However, a VRR may exhibit poor compensation performance at high-frame rates and high flicker levels at low-frame rates [5].

Deterioration of compensation performance in high-frame rates causes luminance non-uniformity. As the required frame rate increases, the scan time (t_SCAN) of one row is shortened; the compensation time (t_COMP) is now too short to reduce the threshold voltage (V_TH) variation, and compensation performance deteriorates. The pixel circuits in one row can acquire voltages from only the data lines within the t_SCAN. Therefore, a short t_SCAN may cause the t_COMP to be too short for the voltage programming method, resulting in the compensation error for luminance non-uniformity [2,6,15]. If the stored voltage is not exactly equal to the real V_TH of the driving TFT (D-TFT), the voltage-programmed pixel circuits are prone to imperfect compensation due to the limited t_SCAN available. In other words, to ensure the image quality of a high-frame-rate display, t_COMP should not be limited by t_SCAN. However, in most pixel circuits of the voltage programming method, t_COMP, and t_SCAN are identical [7–10]. To overcome this issue, some pixel circuits have been developed to extend t_COMP [11–16], but these pixel circuits are based on LTPS TFTs and thus cannot be driven at low-frame rates. Therefore, it is necessary to extend t_COMP without affecting the frame rate.

Flicker is crucial in low-frame rate driving; the lower the frame rate, the longer the time to hold data on the storage capacitor. When the pixel circuits operate at low-frame rates, the V_GS values of the D-TFTs change because of the leakage current of the switching TFTs [17]. These V_GS values directly influence the OLED current during emission, resulting in flicker. In other words, the leakage current of a switching TFT limits the applications of low-frame rate-driven displays. Many researchers have investigated overcoming this issue [5,18–20]. Unlike LTPS TFTs, indium-gallium-zinc-oxide (IGZO) TFTs enable low-frame rate driving due to their extremely low leakage current [17]. Hence, several pixel circuits using LTPO TFTs have been developed for low-frame rate driving [5,19–30]. However, in the LTPO TFTs-integrated pixel circuit, the D-TFTs’ hysteresis based on LTPS remains challenging [5]. The perceived luminance change induced by D-TFT hysteresis is less visible at conventional frame rates (e.g. 60 Hz). However, driving a pixel circuit at a low-frame rate increases its sensitivity to the dynamic behavior of D-TFTs (i.e. hysteresis) [5]. When a display is driven at a low-frame rate, the D-TFT current should stabilize as quickly as possible during image changes to minimize perceived luminance fluctuations (i.e. flicker). During low-frame rate driving, flicker is caused not only by the leakage current of the switching TFT but also by D-TFT hysteresis. This hysteresis is attributable to carrier trapping or detrapping, which affects V_TH and causes transient luminance variations [21]. The mechanism can be described as follows:

Figure 1. Schematic I-V characteristic of p-type TFT: The solid black line is the I-V curve when changing from V_TH sampling to data programming period, and the dotted blue line is the I-V curve during the emission period.

First step (V_TH sampling): The solid black line in Figure 1 represents the D-TFT I-V curve during the V_TH sampling and programming period. The V_TH [point (1)] is sampled at this time, and V_GS [point (2)] is programmed based on the sampled V_TH and data voltage (V_DATA). Therefore, emission begins with desired OLED current I_{DS_(2)}, providing the desired luminance.

Second step (emission period): Figure 1 shows that after V_DATA programming, stress applied to the D-TFT changes the TFT I-V characteristics from I_{DS_(2)} to I_{DS_(3)} because of D-TFT hysteresis, changing the luminance. The transient luminance change caused by D-TFT hysteresis does not create a visible flicker at conventional frame rates (e.g. 60 Hz) because the perceived luminance fluctuation is well below the flicker fusion threshold [22]. Under low-frame rate driving, however, it is critical to minimize the luminance fluctuation over time because the sensitivity of humans to flicker increases greatly from 10 to 15 Hz [23]. As might be expected, the larger the hysteresis, the greater the luminance fluctuation and the more perceptible the flicker under low-frame rate driving. For this reason, low-frame rate driving requires that the leakage currents of the switching TFTs are low, and the hysteresis of the D-TFT is small. However, hysteresis is an intrinsic feature of an LTPS TFT [24]. Therefore, for low-frame rate driving of an LTPO TFT-based AMOLED display, a new driving scheme that can compensate for D-TFT hysteresis is required.

In this paper, we propose a novel pixel circuit extending t_COMP without affecting the frame rate. Extension of t_COMP for each row guarantees accurate detection of V_TH variations in D-TFTs. Also, the proposed driving scheme can compensate for the hysteresis of D-TFTs and supports low-frame rate flicker-free driving. Simulations were conducted, and a 6.0-inch quad high-definition (QHD) LTPO based AMOLED display was fabricated to verify the new pixel circuit and driving scheme. The manufactured AMOLED display exhibited excellent image quality during high-frame rate driving and no visible artifacts during low-frame rate driving.

Figure 2. (a) Proposed pixel circuit and its timing diagrams of control signals in (b) refresh frame and (c) skip frame.

2. Operation of the proposed pixel circuit

Figure 2(a) illustrates the proposed pixel circuit composed of one D-TFT, five switching TFTs, and two capacitors. Figure 2(b) and (c) present the timing diagrams of the control signals for the refresh and skip frames, respectively. The refresh and skip frames constitute one frame during low-frame rate driving [25]. Data are sequentially noted during the refresh frame period; no data are written during the skip frame period. DV(n), a dynamic voltage, provides the initialization voltage (V_INT) and on-bias voltage (OBV) for hysteresis compensation to the refresh and skip frames, respectively. The OBV is always higher than V_DATA. During the skip frame period, the S1 and S2 gate drivers output low voltage, and the clocks do not toggle; this reduces the power consumption of gate drivers. OBV is applied to the D-TFT to compensate for hysteresis during the skip frame period. Of the five switching TFTs, T1 and T2 are oxide TFTs, which is important because the gate voltage (V_G) of the D-TFT changes, and the flicker degrades the image quality if the leakage current of the switching TFT connected to the gate of the D-TFT is large. Figure 2 displays the proposed pixel circuit operation divided into six stages.

Figure 3(a) shows the anode reset stage (t_A/R), where S3(n) and EM(n−1) are under low voltage and turn on T3 and T5. This stage aims to improve the low gray non-uniformity [26]. V_INT is equal to V_SS or less than the OLED turn-on voltage to prevent current flow through the OLED when a black image is required.

Figure 3. Schematic of pixel circuit operation in (a) anode reset (t_A/R), (b) initialization (t_INT), (c) compensation (t_COMP), (d) data program (t_PROG), (e) emission, and (f) t_OBV in skip frame period.

Figure 3(b) demonstrates the initialization stage (t_INT), where S1(n) is under high voltage to turn on T1, and EM(n) is under low voltage to turn on T4. The S2(n) voltage is low to turn off T2, and the S3(n) and EM(n−1) voltages are high to turn off T3 and T5. This stage initializes the voltages of the gate and source nodes of the D-TFT. The gate node (N2) and source node (N1) of D-TFT are initialized to V_REF and V_DD, respectively. As T5 is turned off during the initialization stage, the OLED is completely off and achieves the real black luminance.

Figure 3(c) details the compensation stage (t_COMP), where the EM(n) goes high to turn off T4. The S1(n) voltage remains high to apply V_REF to N2. S3(n) goes low to turn on T3. V_{GS_D-TFT} is larger than |V_{TH_D-TFT}|; the D-TFT begins to generate a current. Meanwhile, N1 discharges through T3 until the D-TFT is cut off. Finally, N1 discharges to V_REF + |V_{TH_D-TFT}|, as follows: (1) $\begin{array}{rl}{V}_S\left(=N1\right)& =V_{REF}+|V_{TH\mathrm{\_}D-TFT}|,\\ V_G\left(=N2\right)& =V_{REF}\end{array}$(1)

In this stage, S2(n) remains low to turn off T2, so the proposed compensation scheme does not require any voltage from the data lines. Therefore, the t_COMP of V_TH is not limited by t_SCAN, and the t_COMP values of multiple rows can overlap, as shown in Figure 4. This increases the total t_COMP available for sensing V_{TH_D-TFT} and thus improves the precision of sensing. Hence, the pixel circuits maintain the D-TFT drain currents (I_DS) uniform because the V_TH variations of the D-TFT are well-compensated. The proposed pixel circuit generates a uniform driving current even during high-frame rate driving. So, this pixel circuit can improve the motion image quality of displays. In addition, T5 is turned off, and V_INT is smaller than V_SS; thus, all currents generated by the D-TFT flow into the DV line rather than the OLED. The OLED remains completely dark.

Figure 4. The extended t_COMP using overlapping scheme when (a) t_COMP is 2H and (b) t_COMP is 4H.

Figure 3(d) shows the data programming stage (t_PROG) in which S2(n) is high to turn on T2, and V_DATA is applied to N2. V_DATA is stored in a capacitor (C1), and the source voltage of the D-TFT is boosted as follows: (2) $\begin{array}{rl}{V}_S& =V_{REF}+|V_{TH\mathrm{\_}D-TFT}|\\ & +\left(V_{DATA}-V_{REF}\right)\cdot \left\{C1/(C1+C2)\right\}\end{array}$(2) where V_S is the source voltage of the D-TFT, and V_REF is the reference voltage.

Figure 3(e) exhibits the emission stage, where S1(n) and S2(n) go low to turn off T1 and T2. EM(n) and EM(n−1) go low to turn on T4 and T5; thus, and V_DD is applied to N1. The V_G of the D-TFT is boosted as follows: (3) $\begin{array}{rl}{V}_G& =V_{DATA}+[V_{DD}-V_{REF}-|V_{TH\mathrm{\_}D-TFT}|\\ & -\left(V_{DATA}-V_{REF}\right)\cdot \left\{C1/(C1+C2)\right\}]\end{array}$(3) where V_G is the gate voltage of the D-TFT. The OLEDs of all pixels in a row begin to emit. The OLED current (I_OLED) is: (4) $\begin{array}{rl}{I}_{OLED}& =\frac{1}{2}k[V_{DD}-(V_{DATA}+V_{DD}-V_{REF}\\ & -|V_{TH\mathrm{\_}D-TFT}|)-(V_{DATA}-V_{REF})\\ & \cdot \left\{C1/(C1+C2)\right\}-|V_{TH\mathrm{\_}D-TFT}|{]}^2\\ & =\frac{1}{2}k\left[\right(V_{REF}-V_{DATA})\cdot \{C2/(C1+C2)\}{]}^2\end{array}$(4) where $k$ is the µ·C_OX·W/L of the D-TFT. In Eq. (4), V_{TH_D-TFT} and V_DD are eliminated; D-TFT V_TH variations and I-R drop since the resistance of the V_DD metal line will not influence the uniformity of the display image. Therefore, the proposed pixel circuit generates a uniform driving current, and the t_COMP of V_TH is not limited by t_SCAN.

Figure 5. Schematic of the dynamic behavior of the D-TFT due to the hysteresis characteristics: (a) I-V curve (dotted red line) during emission and (dotted blue line) during OBV and (b) schematic of I_DS change before and after OBV.

In the hysteresis compensation stage (t_OBV), OBV is applied during the skip frame period to compensate for D-TFT hysteresis and minimize flicker. Figure 3(f) points out that in this stage, S3(n) goes low to turn on T3; OBV is applied to N1 via N3. The OBV is higher than N2 and the programmed V_DATA. OBV time (t_OBV) is 50 µs. Thus, the V_GS of the D-TFT remains on status. The mechanism of the proposed driving scheme’s hysteresis compensation can be described as follows:

After V_TH sampling and V_DATA programming, bias stress is applied to the D-TFT to change the V_TH, resulting in the luminance fluctuations, as shown in Figure 1. I_DS shifts from point (2) on the thick solid black line to point (3) on the thin dotted red line, as shown in Figure 5(a) and is shown on the time axis of the solid black line in Figure 5(b). To compensate for D-TFT hysteresis, OBV is applied to the D-TFT during the skip frame. This shifts I_DS_(3) to I_DS_(4), while V_{TH­­_D-TFT} shifts positively. The voltage applied to the D-TFT changes the TFT I-V curve from the thin dotted red line to the thick dotted blue line. After OBV application, a bias stress opposite to that during programming and V_TH sampling is applied to the D-TFT; the TFT I-V curve then moves from point (4) to point (5) along the thick dotted blue line in Figure 5(a). This is explained by the time axis, as shown in the blue dotted line in Figure 5(b). Therefore, the current increase from point (2) to point (3) after programming and V_TH sampling is offset by the current drop from point (5) to point (3) after applying the OBV, thereby reducing the current change. Thus, flicker is not perceived during low-frame rate driving. Applying the OBV during the skip frame reduces the deviation between the current-decrease area (A: blue slanted area) after applying the OBV and the current-increase area (B: black mesh).

Figure 6. I-V characteristics of fabricated LTPS D-TFT and oxide switching TFT.

3. Results and discussion

SmartSpice (Silvaco Inc.) simulations were conducted, and a 6.0-inch QHD LTPO-based AMOLED display was fabricated to confirm that the proposed pixel circuit provided uniform luminance at 120 Hz and QHD resolution. The frame rate ranges from 1 to 120 Hz VRR driving. Although most smartphones still use full high-definition (FHD) resolution, the newest premium smartphones provide QHD (or even higher) resolution. Mobile devices with frame rates of 120 Hz are not yet widely available, especially mobile LTPO-based AMOLED displays.

The researchers simulated the proposed pixel circuit with QHD and a maximum frame rate of 120 Hz for future mobile applications. Figure 6 shows the I-V characteristics of fabricated LTPS D-TFTs, with aspect ratios of 3.0 µm / 16.0 µm and oxide TFTs, with 3.0 µm / 3.5 µm aspect ratios, as used in the simulations. Table 1 lists the parameters of the fabricated TFTs employed in simulations. Table 2 outlines the capacitance, scan signals, and voltage levels simulated.

Table 1. Parameters of the fabricated LTPS and oxide TFT.

TFT Parameters
	LTPS TFT	Oxide TFT
W/L (µm)	3.0 / 16.0	3.0 / 3.5
VTH (V)	−3.18	0.34
Subthreshold Slope (V/dec)	0.52	0.10
Mobility (cm^2/V·s)	75.2	18.9

Table 2. Simulation conditions

Pixel simulation conditions
C1 (fF)	40
C2 (fF)	10
S1∼S3, EM (V)	10.0 ∼ −10.0
VDD, VSS (V)	7.5, 0.0
VREF (V)	3.5
OBV (V)	3.0∼3.5
tOBV (µs)	30
VINT (V)	0.0∼0.5

Figure 7. Simulated transient waveforms of the gate (N2) and source node (N1) of D-TFT according to t_COMP; (a) Input waveforms of S1 according to t_COMP, and V_GS of D-TFT waveforms when t_COMP is (b) 2.0, (c) 4.0, and (d) 8.0 µs.

3.1. Compensation performance during high-frame rate

Figure 7(a) shows the input signal waveform of the S1 gate driver as t_COMP is varied from 2.0 µs to 8.0 µs. Figure 7(b) to (d) show the simulation results when D-TFT V_G (N2) and V_S (N1) change at t_COMP value of 2.0 µs, 4.0 µs, and 8.0 µs, respectively. At this time, t_PROG is fixed at 2.0 µs. In a conventional driving scheme, t_PROG and t_COMP are identical; the t_COMP values of FHD and ultra-high-definition (UHD) at 120 Hz frame rate are 8.0 µs and 2.0 µs, respectively. When t_COMP is 2.0 µs and 4.0 µs, the V_GS values of the D-TFT are −4.10 V and −3.69 V after D-TFT V_TH sensing, as shown in Figure 7(b) to (c), respectively. When t_COMP is 8.0 µs, the D-TFT V_GS is −3.28 V, as shown in Figure 7(d). As the simulated D-TFT V_GS is −3.18 V, with longer t_COMP, the D-TFT V_GS becomes more similar to V_TH. As t_COMP becomes longer, V_GS converges to the D-TFT V_TH. From these simulation results, the longer t_COMP allows more precise sensing of D-TFT V_TH variations. Figure 8 shows the relative I_OLED error rates versus the D-TFT V_TH variations of −3.0 V ± 0.1 V ∼ ± 0.5 V at 5 gray (0.2 nits) corresponding with different t_COMP. The relative I_OLED error rate ranges from −28.6% to 26.4%, −16.2% to 15.6%, and −6.2% to 6.6% for t_COMP of 2.0, 4.0, and 8.0 µs, respectively, confirming that the proposed pixel circuit with the longest t_COMP of 8.0 µs indeed compensates more effectively for the D-TFT V_TH variations. Also, the pixel circuit can freely extend t_COMP owing to its overlapping compensation scheme. The luminance uniformity of the manufactured 6.0-inch LTPO-based AMOLED display was measured to evaluate the compensation performance of the pixel circuit with various t_COMP values. Figure 9(a) to (c) present the optical images when t_COMP was 2.0, 4.0, and 8.0 µs, respectively. As t_COMP increases, the luminance uniformity improves. An ultra-high-resolution camera (RADIANT SOLUTION FPiS^TM) was used to quantify uniformity. The measured luminance was 0.2 nits at 5,000 points within the panel. As a result of measuring local luminance uniformity, the standard deviations of luminance became smaller as t_COMP became longer (0.056, 0.024, and 0.008 for t_COMP values of 2.0, 4.0, and 8.0 µs, respectively), as shown in Figure 9(d) to (f). These results confirm that the simulation results provide accuracy for the measurement results of luminance uniformity. Since the proposed pixel circuit can increase the t_COMP, even if t_PROG (or t_SCAN) is short as the frame rate increases, the compensation performance can secure the same level as the FHD panel because the t_COMP of FHD is 8.0 µs. Therefore, the proposed pixel circuit ensures excellent luminance uniformity even at 120 Hz QHD high-frame rate driving. Also, as the pixel circuit can be driven at 120 Hz, the moving image quality of the AMOLED display can be improved [27–29].

3.2. Flicker characteristics of low-frame rate

Since the lower the frame rate, the longer the skip frame period compared to that of high-frame-rate driving, the time to hold the programmed data also becomes longer. If the voltage-holding characteristic of the programmed data is poor during one frame, a flicker occurs. Therefore, the holding characteristics of V_DATA are improved by applying oxide TFTs with very low leakage current to switching TFTs [15]. Fig. S4(a) shows almost no luminance fluctuation at 120 Hz; flicker is not recognized. However, although the leakage current was reduced by using oxide TFT, luminance fluctuations were still present within one frame at a low gray level during 10 Hz driving. Consequently, flicker was perceived in panels fabricated from LTPO TFTs due to luminance drop at 10 Hz driving, as indicated in Figure 13(a). This luminance drop during the emission period is due to the D-TFT hysteresis. Figure 1 explains the flicker mechanism, where the larger the D-TFT hysteresis, the greater the luminance change. Furthermore, flicker becomes more visible under low-frame rate driving [23]. However, if the D-TFT hysteresis is small and settles rapidly, the magnitude and duration of luminance fluctuation are reduced, and flicker is less perceivable. Therefore, it is essential to minimize hysteresis to support low-frame rate driving. The proposed new driving scheme can compensate for D-TFT hysteresis. Figure 10(a) demonstrates the low-frame rate driving, divided into refresh and skip frames. Although no data are programmed during the skip frame, the OLED emits light. As highlighted in Figure 10(a), the proposed driving method supports flicker-free display low-frame rate driving; the OBV applied to the D-TFT during the skip frame compensates for hysteresis as follows. The D-TFT V_TH positively shifts after OBV is applied during the skip frame. A negative shift of the D-TFT V_TH during the refresh frame, and a skip frame with OBV, can be compensated for by the OBV. Figure 10(b) shows the D-TFT V_TH behavior when OBV is applied during the skip frame period. Simulations were conducted to verify the proposed driving scheme. Figure 11(a) exhibits the simulation result that D-TFT V_TH is negatively shifted because of hysteresis during the skip frame period when OBV is not applied when driving at 10 Hz. Figure 11(b) also shows the simulation result that D-TFT V_TH is positively shifted during the skip frame period when OBV is applied during driving at 10 Hz. From the simulation results, if OBV is applied in the skip frame period, the negative shift of D-TFT V_TH is reduced due to the relatively positive shift of D-TFT V_TH. Figure 11(c) reflects the simulation result that I_OLED changes when OBV is not applied during 10 Hz driving. As in Figure 11(a), D-TFT V_TH fluctuation increases, as does the I_OLED change. Figure 11(b) reveals that when OBV is applied, the fluctuation of D-TFT V_TH’ is decreased, as is the I_OLED change, as shown in Figure 11(d). Same as the 10 Hz simulations, the simulations were performed at 1 Hz depending on whether OBV was applied or not. Figure 12(a)-(b) explains that D-TFT V_TH is negatively shifted during the skip frame period when OBV is not applied but not when OBV is applied when driving 1 Hz. From the simulation results, if OBV is applied during the skip frame period, the negative shift of D-TFT V_TH is reduced by a relatively positive shift in D-TFT V_TH. Figure 12(c) confirms I_OLED changes when OBV is not applied during 1 Hz driving. Figure 12(a)’s results suggest that when OBV is not applied, the fluctuation of D-TFT V_TH is increased, and the I_OLED change also increases, as shown in Figure 12(c). Figure 12(b)’s results imply that when OBV is applied, the fluctuation of D-TFT V_TH is decreased, and the I_OLED change also decreases, as shown in Figure 12(d). Therefore, the OBV driving scheme is essential for the LTPO pixel circuit that can control the V_TH behavior of D-TFT. A 6.0-inch QHD LTPO-based AMOLED display is fabricated to verify the proposed pixel circuit and new driving scheme, and luminance measurements were performed with the MINOLTA CA-410. Figure 13(a) and (b) show the measurement results of luminance fluctuation without and with OBV during 10 Hz driving, respectively. Figure 13(a) presents that if OBV was not applied, the luminance fluctuation was 3.0% between frames. Such luminance fluctuation causes visible artifacts, that is, flicker. However, when OBV was applied, the luminance fluctuation was 0.5%. Figure 13(c) and (d) show the measurement results without and with OBV during 1 Hz driving, respectively. Figure 13(c) represents that when OBV was not applied, the luminance fluctuation was 2.8% between frames. When OBV is applied, the luminance fluctuation was 1.0%. Therefore, no visible artifacts are perceived, and flicker is not recognized. Figure 12 conveys that the measurement results are consistent with those of the simulation. Based on these results, Figure 14 shows the results of flicker measurement when OBV is applied and not applied using the FLICKER MODE of MINOLTA CA-410. During 10 Hz driving, the flicker was −15 dB when no OBV was applied; this value is highly perceptible. However, when OBV was applied, both 1 Hz and 10 Hz driving showed the flicker was no higher than −50 dB, and no artifacts were perceived. These results proved that the causes of flicker of LTPO-based AMOLED pixel circuit in the low-frame rate driving are the leakage current of the switching TFTs and D-TFT hysteresis. Also, it is proved that the proposed compensation pixel circuit and driving scheme operate stably at high- and low-frame rates, so full VRR driving can be implemented. Figure 15 shows the measurement result of power consumption according to frame rate. The condition of power consumption measurement is 40% turn-on at 500 nits with a 6.0-inch QHD panel. The power consumption decreases as the frame rate decreases, and when driving at 1 Hz, the power consumption of the driver IC block (including analog and logic) is reduced by a quarter compared to that of the 120 Hz frame rate driving. The reason for the reduction in power consumption is that output signals of data and some gate drivers are not operated during the skip frame period when driving at a low-frame rate, as indicated in Figure 10(a). However, the power consumption of the panel does not decrease because the frame rate does not affect the D-TFT current. Based on the measurement results, the LTPO-based AMOLED display provides excellent moving image quality and low power consumption through the VRR driving depending on the operation environment(e.g. game, AOD, still image, and text mode).

Figure 8. Simulated relative I_OLED error rates at ΔV_{TH_D-TFT} = ±0.1 V, ± 0.2 V, ± 0.3 V, ± 0.4 V, ± 0.5 V according to t_COMP; t_COMP is 2.0, 4.0, and 8.0 µs.

4. Comparison to previous works

Table 3 compares the new pixel circuit with previous ones. The circuits in [2,6,30,31] have t_COMP values larger than the t_SCAN values. However, the pixel circuits in [2,6], and [32] cannot compensate for VDD IR drop, so they cause upper and lower luminance deviation in the display panel. The pixel circuit of [30] lacks high-resolution capability because it requires two data lines. Also, none of these circuits compensates for hysteresis. They cannot operate at low-frame rates as they are composed only of LTPS TFTs. Pixel circuits based on LTPO [32,33] do not compensate for hysteresis and cannot extend the t_COMP. Therefore, even with LTPO pixel circuits, a flicker occurs during low-frame-rate driving, and compensation performance deteriorates due to the reduced t_COMP during high-frame-rate driving. The proposed pixel circuit and driving scheme can achieve VRR driving from 1 to 120 Hz.

Figure 9. The optical image of a 6.0-inch LTPO-based AMOLED display when t_COMP is (a) 2.0, (b) 4.0, and (c) 8.0 µs, and measured luminance uniformity of 100 × 50 pixels area when t_COMP is (d) 2.0, (e) 4.0, and (f) 8.0 µs.

Figure 10. The conceptual schematic of (a) timing diagram of the OBV driving at low-frame rate and the (b) V_TH behavior of D-TFT when OBV is applied.

Figure 11. Simulation results of D-TFT V_TH behavior and I_OLED fluctuation according to the OBV at 10 Hz: (a) D-TFT V_TH behavior without OBV, (b) D-TFT V_TH behavior with OBV, (c) I_OLED variation without OBV during skip frame, and (d) I_OLED variation with OBV during skip frame.

Figure 12. Simulation results of D-TFT V_TH behavior and I_OLED fluctuation according to the OBV at 1 Hz (a) D-TFT V_TH behavior without OBV, (b) D-TFT V_TH behavior with OBV, (c) I_OLED variation without OBV during skip frame, and (d) I_OLED variation with OBV during skip frame.

Figure 13. Measurement results of luminance fluctuation (a) without OBV at 10 Hz, (b) with OBV at 10 Hz, (c) without OBV at 1 Hz, and (d) with OBV at 1 Hz.

5. Conclusion

This paper presents a novel pixel circuit and driving scheme based on an LTPO TFT backplane. This extends the t_COMP. The pixel circuit overlaps the t_COMP of multiple rows, which increases the V_TH sensing time and allows precise extraction of D-TFT V_TH variations. A novel pixel driving scheme that compensates for the hysteresis by applying OBV to the D- TFT was proposed and experimented to ensure flicker-free display during low-frame rate driving. A 6.0-inch QHD LTPO-based AMOLED panel is fabricated, and the fabricated panel exhibits excellent luminance uniformity. Measurement results of luminance uniformity of the proposed pixel circuit show that the standard deviation of luminance was reduced from 0.056 to 0.008 by extending the t_COMP from 2 to 8 µs. The proposed pixel circuit exhibits excellent compensation performance of D-TFT V_TH variations even during high-frame-rate driving with a short t_SCAN. Also, applying OBV to the D-TFT greatly reduces flicker at 1 and 10 Hz. The flicker level was –51 dB, without any visual artifacts, during 1 Hz driving. Compared to 120 Hz, the power consumption of the driver IC is reduced by a quarter at 1 Hz. Therefore, the proposed pixel circuit and driving scheme based on the LTPO TFT backplane can operate without visual artifact in VRR driving from 1 to 120 Hz and can be used in the LTPO-based AMOLED display for mobile devices.

Figure 14. Flicker measurement results without and with OBV according to the frame rate.

Figure 15. Measurement results of power consumption according to the frame rate.

Table 3. Comparison of the proposed pixel circuit and other works.

Reference	Hysteresis compensation (OBV)	tCOMP extension	Anode reset	High resolution	VDD IR drop compensation
[2] 6T2C	X	O	O	O	X
[6] 6T2C	X	O	O	O	X
[30] 6T1C	X	O	X	X	O
[31] 7T2C	X	O	O	O	X
[32] 7T1C	X	X	O	O	X
[33] 7T1C	X	X	O	O	X
This work (6T2C)	O	O	O	O	O

Disclosure statement

No potential conflict of interest was reported by the author(s).

Additional information

Funding

This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government. (NRF-2021R1A4A1031437).

Notes on contributors

Jung Chul Kim

Jung Chul Kim received the M.S. degree from the Department of Information Display, Kyung Hee University, Seoul, South Korea, in 2003. He is currently pursuing his Ph.D. degree at the School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea. He is also currently a Research Fellow on mobile OLED panel design with the Mobile Business Unit, LG Display, Paju, Korea. His current research interests include the OLED compensation pixel circuit and advanced technology of flexible display panel.

I. Sak Lee

I. Sak Lee received his Ph.D. degree from the School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea, in 2022. He is also a Senior Research Engineer in the OLED panel devices development team with the TV Business Unit, LG Display, Paju, Korea. He has been researching high-performance n-type oxide TFTs and their application to phototransistors.

Hyung Tae Kim

Hyung Tae Kim received his B.S. degree from the Department of Electronic Engineering, Chung-Ang University, Seoul, South Korea, in 2018. He is also currently a Ph.D. candidate at the School of Electrical and Electronic Engineering at Yonsei University, Seoul, South Korea. He has been researching an application based on oxide TFTs, including neuromorphic devices and photosensors.

Jong Bin An

Jong Bin An received his B.S. degree from the School of Electrical and Electronic Engineering at Yonsei University, Seoul, South Korea, in 2020. He is currently a Ph.D. candidate at the same institute. He has been researching high-performance n-type oxide TFTs and their application to phototransistors.

Jae Sung Kim

Jae Sung Kim received his B.S. degree from the Department of Electrical Engineering, Kyung Hee University, Gyeonggi-do, South Korea, in 2010. He is also a Senior Research Engineer in mobile OLED panel design with the Mobile Business Unit, LG Display, Paju, Korea. His current research interests include the OLED compensation pixel circuit.

Juhn Suk Yoo

Juhn Suk Yoo received his M.S. and Ph.D. degrees from the School of Electrical and Electronic Engineering, Seoul National University, Seoul, South Korea, in 1997 and 2001, respectively. He is currently a Chief Research Fellow of the Mobile Business Unit, LG Display, Paju, Korea. His research interests are LTPS and oxide TFT for AMOLED mobile display applications. He is also interested in advanced technology of flexible display panel.

Han Wook Hwang

Han Wook Hwang received his Ph.D. degree from the School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea, in 2019. He is currently a Vice President of the Mobile Business Unit, LG Display, Paju, Korea. His research interests are LTPS and oxide TFT for AMOLED mobile display applications. He is also interested in the development of flexible display applied with AMOLED.

Hyun Chul Choi

Hyun Chul Choi received his M.S. and Ph.D. degrees from the Department of Chemistry, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in 1991 and 1994, respectively. He is currently a Senior Vice President of the Mobile Business Unit, LG Display, Paju, Korea.

Yong Min Ha

Yong Min Ha received his M.S. and Ph.D. degrees from the Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in 1990 and 1994, respectively. He is currently an Executive Vice President of the Quality Management Center, LG Display, Paju, Korea.

Hyun Jae Kim

Hyun Jae Kim received his Ph.D. degree from the Department of Materials Science and Engineering, Columbia University, New York City, NY, USA, in 1996. Since 2005, he has been a Professor with the Faculty of the School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea.