Recent progress in the development of backplane thin film transistors for information displays

Abstract

This review aims to provide a technical roadmap and an overview of recent progress in the development of backplane thin film transistors (TFTs) for organic light-emitting diodes flat panel displays and next-generation flexible displays. In the introduction, we provide a general overview of the research trends for backplane TFTs. The main part describes the current technical level and prospects for amorphous metal oxide semiconducting, metal halide perovskites, and 2D transition metal dichalcogenides TFTs. The summary and prospects are provided in the conclusion section.

KEYWORDS:

• Thin-film transistor
• flat panel display
• oxide semiconductor
• metal halide perovskite
• two-dimensional van-der Waals semiconductor

1. Introduction

Optimizing materials and manufacturing processes for backplane thin film transistors (TFTs) has been crucial in advancing and enhancing Flat Panel Displays (FPDs). TFTs are the fundamental building blocks of FPDs, controlling current flow and operating the display pixels. In the past, TFTs made of amorphous silicon (a-Si) were used in backplane circuits in liquid crystal displays. However, these TFTs were limited in their application to organic light-emitting diode (OLED) displays. New TFT technologies were needed to support higher current values and stable operation. Low-temperature polycrystalline silicon (LTPS) TFTs were developed and successfully used in OLED displays to meet these requirements. Despite these advances, high-power consumption and poor performance uniformity over large areas remained the limitations of using LTPS TFTs in large-area display applications such as OLED TVs [1–5].

Amorphous metal oxide semiconductors, such as indium gallium zinc oxide (IGZO), are widely used as OLED driving circuits due to their cheap manufacturing cost, high-performance uniformity, and low off-state current [6]. However, the low mobility of these transistors needs to be improved for scaling up to high-resolution displays. One solution to this challenge is LTPO technology, which combines the advantages of metal oxide and LTPS TFTs. However, LTPO technology has a slightly more complicated manufacturing process and higher process cost than the existing technology that implements a backplane with one transistor type. Therefore, further improvements in the performance of oxide transistors are necessary to overcome this problem.

Perovskite and 2D transition metal dichalcogenides (TMDCs) materials are emerging semiconducting materials for a channel of TFTs, offering several advantages over traditional TFT materials, including high carrier mobility, low power consumption, and improved operational stability. Although perovskite and TMDCs TFTs are still in the early stages of development, they need to improve various aspects of performance, including processability and stability. Despite their potential, material toxicity, device hysteresis, and perovskite material stability are major challenges that need to be overcome for commercialization on a wide scale [7]. 2D TMDCs channel can be uniformly affected by the gate voltage, confining all electrons in an atomically thin layer. However, contact resistance (R_c) caused by defects of the TMDC surface in the conventional metal electrode formation process is a main challenge for TMDCs transistors [8]. In addition, the lack of a process to achieve uniform device performance over a large area, such as in display, also needs to be overcome. Various attempts are being made to improve the perovskite’s stability and reliability and TMDCs TFTs’ contact resistance, and it is expected that they could become a viable option for use in FPDs in the future.

This review provides recent progress in the development of backplane TFTs for flat panel displays and next-generation displays, such as flexible and rollable mobile phones or TVs. This article introduces various research efforts to improve the mobility and stability of n-type oxide TFTs and the recent research development based on perovskite and 2D TMDC materials. The purpose is to provide an overview of the direction of the new materials and their potential to enhance performance.

2. Metal oxide TFTs

Since binary oxide semiconductor materials, including SnO₂ and In₂O_3, were introduced as channel layers of TFTs in 1964 [9], research on oxide semiconductors has led to the development of multi-component oxide semiconductors such as In-Ga-Zn-O with various advantages. Up to now, amorphous metal oxide semiconductor-based TFTs have drawn considerable attention due to their many advantages, such as high mobility compared to a-Si, transparency, and large area uniformity [10]. Based on these characteristics, research related to this section has been conducted to achieve higher mobility and excellent stability for application to high-end displays with a large area, high resolution and high PPI.

In this regard, the research summary of n-type oxide TFTs (Table 1, Figure 1) is organized in the following parts: (1) modification of metal chemical composition by atomic layer deposition (ALD) process; (2) high-performance TFTs through induction of crystallization; and (3) mobility enhancement effect of various metal capping layers. In addition, research for the realization of high-performance p-type oxide TFTs (Table 2) is discussed.

Figure 1. Field-effect mobility trends depending on the process temperature of various thin-film transistors.

Table 1. Recent representative research of n-type metal oxide-based TFTs.

Type	Method	Material	Process temp. (°C)	${\mu }_{FE}$ (cm^2/Vs)	S.S. (V/dec)	Ion/Ioff	Ref.
n-type	Chemical Composition	IGZO	250	74.0	0.13	2.6 × 10^8	[1–5]
		IGZO	200	74.3	0.26	8.9 × 10^8	[6]
		IGZO	250	48.3	0.45	∼ 10^7	[7]
		IGO	700	60.7	0.40	5.1 × 10^9	[8]
		ZnO/IGO	250	63.2	0.26	9.0 × 10^8	[11]
	Crystallization	IGZO	300	54.0	0.3	4.4 × 10^7	[12]
		IGO:H	250	50.6	0.1	–	[13]
		In2O3:H	250	142	0.41	–	[14]
		IGO	200	56	0.1	–	[15]
		IGTO	400	116.5	0.134	3.3 × 10^9	[16]
	Metal Capping Layer	IGZO	300	54.0	0.30	4.4 × 10^7	[12]
		IGZO	430	46.7	–	4.9 × 10^8	[17]
		SZTO	500	147.6	0.32	6.2 × 10^8	[18]
		SZTO	500	37.8	0.28	3.0 × 10^9	[19]
		IZO	300	61.0	0.11	2.3 × 10^8	[20]
		ZnON	250	89.4	0.33	8.6 × 10^8	[21]
		ZTO	500	70.8	0.19	2.0 × 10^8	[22]
		IGZO	350	105.7	0.12	9.7 × 10^8	[23]
		ZBTO	350	153	0.37	∼ 10^9	[24]

Table 2. Recent representative research of p-type metal oxide-based TFTs.

Type	Material	Process temp. (°C)	${\mu }_{FE}$ (cm^2/Vs)	S.S. (V/dec)	Ion/Ioff	Ref.
p-type	SnO	200	4.4	0.526	2 × 10^5	[25]
	SnOX	300	6.0	4.6	2.7 × 10^2	[26]
	Ga:Cu2O	800	0.74	7.72	1.22 × 10^4	[27]
	CuOX	300	5.64	0.75	1.79 × 10^5	[28]
	NiOX	300	∼25	0.7	∼ 10^5	[29]
	Li:NiOX	150	1.69	0.21	8 × 10^6	[30]
	Cu:NiO	150	1.53	0.13	∼ 10^4	[31]
	β-TeO2	270	232	0.103	> 10^6	[32]
	Te	−80	35	0.108	∼10^4	[33]
	Te	150	30.9	6.5	5.8 × 10^5	[34]

Among the various deposition methods of oxide semiconductors, the atomic layer deposition (ALD) process has been attracted significant attention to the deposit of high-quality thin films based on the self-limited chemical reaction between the precursor and the reactant. This method allows easy tuning of the chemical composition, microstructure, and electrical properties, along with excellent step coverage and thickness controllability. According to these advantages, many types of oxide TFTs using the ALD process have high field-effect mobility (20 ≤ μ_FE ≤ 80).

Recent research on ALD-proceed oxide TFTs has reported excellent performance with high mobility and stability by cation composition control. The chemical composition is precisely controlled at the atomic layer level. For example, high mobility properties can be achieved by controlling the subcycle and dosing time of indium-based metal precursors [11–15]. Although the ALD-based process has some drawbacks, such as a slow deposition rate, it presents the feasibility of high-performance devices with complicated 3-dimension structures.

It is a well-known fact that improvement in crystallinity leads to improvement in device mobility. However, the crystallization process requires high temperature, which is unsuitable for glass substrates for display industries or plastic substrates that show low glass transition temperature. Recently, many studies on low-temperature crystallization have been conducted to improve mobility. Shin et al. report the crystallization of IGZO via a tantalum catalytic layer [12]. The Ta layer releases electrons into the underlying IGZO layer, breaking the weak M-O bond. Crystallization occurs during the rearrangement or diffusion of broken M-O bonds during annealing. Attempts have been made to control crystallization by adding hydrogen during deposition [13,14]. By adding hydrogen, crystallization of the oxide semiconductor during deposition can be suppressed by eliminating the nuclei density, and crystallization of oxide film during post-annealing can enlarge the grain size, thus improving mobility. Zn ions stabilize the amorphous network in oxide semiconductors represented by IGZO [15,16]. Accordingly, research on the crystallinity of oxide semiconductors without Zn has been reported. Park et al. detail the high-performance crystallized IGO TFT with a process temperature of 200 °C. By adjusting oxygen partial pressure, low-temperature crystallization is achieved, thus leading to the high mobility of 56 cm²/Vs. IGTO TFTs crystallized at 400 °C have also been reported showing high mobility of 116.5cm²/Vs.

Research on realizing high-performance oxide TFTs through structural modifications such as dual gate [35], passivation [36], and metal capping has been continuously proposed. Compared to other studies, the introduction of metal capping layers can improve the electrical performances of oxide TFTs with various mechanisms, such as electron injection [19,24], conductive region formation [24], and removal of oxygen-related defect state [21,37].

Based on this mechanism, much research on metal-capped oxide TFTs achieved significant mobility enhancement effects (over 100 cm²/Vs) without degrading other transfer parameters. Additionally, this method-maintained device’s reliability has superior electrical performance. Recently, the mobility improvement effect of the metal capping layer was also observed in TFTs with a top-gate structure that is process-compatible with the industries to be applied to next-generation displays [38].

Oxides have difficulty achieving high-performance p-type because carrier conduction mainly occurs in the valence band, formed from oxygen p asymmetrically localized orbitals, limiting carrier mobility. Recently, much attention has been given to SnO-, NiO_x-, and CuO_x-based transistors. Yen et al. claim that a 7 nm thick SnO exhibits field effect mobility of 4.4 cm²/Vs fabricated by the sputtering method with a low process temperature of 200 °C [25]. Also, research on SnO deposition using atomic layer deposition (ALD) with the precursor of N,N′-tert-Butyl-1,1-dimethylethylenediamine stannylene (II) and reactant of deionized (DI) water has been reported. Here, a two-step crystallization process is introduced to grown c-axis oriented SnO and shows the mobility of ∼ 6 cm²/Vs [26].

Copper oxide has two common forms: cuprous oxide or cuprite (Cu₂O) and cupric oxide or tenorite (CuO). Both copper oxides are generally p-type semiconductors, and Cu₂O shows higher mobility than CuO. By doping Ga, which presents high-oxygen affinity, the Cu₂O film decreases oxygen vacancy (V_o) during the reduction [27]. By reduction, Cu₂O TFT improved overall TFT performance, such as field effect mobility, on/off ratio, threshold voltage, and subthreshold swing. Also, there are some reports about copper oxide TFT fabricated by ALD. Wanjoo et al. examine the CuO_x TFT fabricated by the ALD process with the precursor of hexafluoroacetylacetonate Cu(I)(3,3-dimethyl-1-butene)[(hfac)Cu(I)(DMB)] and reactant of ozone gas (O₃) [28]. The XPS results indicate that the Cu²⁺ bonding state increases during the annealing temperature of 300 °C, which means the formation of Cu₂O. Here, the mobility of CuO_x TFT results in 5.64 cm²/Vs.

NiO_x is a promising p-type material due to its good visible transparency, chemical stability, and electrical properties. Shan et al. reveal CuO_x and NiO_x TFTs fabricated by a solution process with various annealing temperatures, with optimum field effect mobility of 0.44 and 0.79 cm²/Vs, respectively. By replacing SiO₂ to high-k Al₂O₃, NiO_x TFTs exhibit high field effect mobility of 25 cm²/Vs [29]. Yang et al. present Li-doped NiOx TFT fabricated with solution-based combustion synthesis and deep-UV treatment. By incorporating Li into the NiO_x matrix, the film’s resistivity and carrier concentration were decreased and increased, respectively. The NiO_x TFT with the optimal Li content exhibits a field effect mobility of 3 cm²/Vs, more than 5 times higher than the control NiO_x TFT [30]. Similarly, Liu et al. investigated Cu-doped NiO_x, where Cu:NiO was fabricated by a solution combustion synthesis with an annealing temperature of 150 ^oC. Cu replaces the Ni sites and generates substituent defects, increasing the p-type conductivity. Optimum Cu:NiO TFTs display a field effect mobility of 1.53 cm²/Vs and an on/off ratio of ∼10⁴ [31].

Tellurium, a two-dimensional material, has recently been reported to have high hole mobility. In 2021, Zavabeti et al. studied β-TeO₂ nanosheets TFT that exhibits high mobility of 232 cm²/Vs and an on/off ratio exceeding 10⁶ [32]. This is a higher value than conventional oxide transistors. Here, β-TeO₂ and Te are considered promising p-type semiconducting materials. In 2020, Te TFTs fabricated by evaporation at -80 °C were reported [33]. Thanks to the vacuum process, a 4-inch wafer scale was achieved, and TFTs showed high mobility of ∼35 cm²/Vs. Also, thanks to the low-temperature process, flexible TFTs on PET substrates were successfully demonstrated. Recently in 2022, Te TFT fabricated by sputtering was also explored [34]. Here, TFT shows high mobility above 30 cm²/Vs and an on/off ratio of 5.8 × 10⁵ with a 4-inch wafer scale. Finally, the CMOS inverter was demonstrated utilizing IGZO and Te TFT, showing a high gain of ∼75.2.

Oxide semiconductors have been studied a lot since the report of IGZO by Nomura et al. Higher mobility is required to meet the demands of modern electronic devices. Unlike high-performance n-type oxide semiconductors with mobility of 100 cm²/Vs or more, securing high-mobility p-type oxide semiconductors is difficult due to localized oxygen 2p orbitals. Various methods have been tried to improve mobility, but the characteristics are still insufficient to be used in the actual backplane of the display, so it still needs to be improved.

3. Metal-halide perovskite TFTs

Metal–halide perovskites (MHPs) are drawing attention as excellent materials for optoelectronic devices, benefiting from their charge transport properties, unique defect tolerance characteristics, and tunable bandgap [39]. Perovskites consist of ABX₃ structure, in which BX₆ octahedra are connected repeatedly in three dimensions, A site is a monovalent cation (MA⁺, FA⁺, Cs⁺), B site is a divalent cation (Pb²⁺, Sn²⁺), and X site is halide anion (Cl^-, Br^-, I^-).

Perovskite can be categorized with many criteria (e.g. the existence of organic A cation, dimension of perovskite structure, B site cation, etc.). All the perovskite has pros and cons. The first perovskite TFT was composed of PEA₂SnI₄ [40], a 2D Ruddlesden-Popper structure rather than the typical 3D perovskite structure of ABX₃. In the case of 2D perovskite, it is slightly better in stability than 3D perovskite. When 3D perovskite is exposed to oxygen or moisture, Pb²⁺ and Sn²⁺ are easily oxidized to Pb⁴⁺ and Sn⁴⁺, respectively. However, in 2D perovskite, A cations between each octahedra layer act as a barrier toward oxygen penetration, resulting in relatively better stability [41].

However, in terms of theoretical performance, 3D perovskite has higher carrier mobility than 2D perovskite because 2D perovskite has limited charge transport and a large bandgap [42]. As a result, many studies on MAPbI₃, which have high efficiency in solar cells, have been conducted [43]. However, Pb perovskite has severe problems, such as toxicity and ion migration. The dominant iodide vacancy has a low migration barrier, so when the gate field is applied, vacancies move toward the field direction and balance out the gate field, which leads to performance degradation. Therefore, the performance of Pb perovskite can be confirmed only when low-temperature or pulsed mode measurement is used [44].

As an alternative to Pb perovskite, Sn perovskite shows great potential. First, Sn is an eco-friendly material relative to Pb [45] and has almost negligible ion migration [46,47]. The dominant vacancy of Sn perovskite is tin vacancy, which has a high migration barrier. Therefore, ion migration is almost negligible. Also, it has very high hole mobility, making it a very suitable material for high-performance transistors. Because of this, research on Sn perovskite is being conducted more actively than before.

In addition, a new structure called double perovskite is also being studied. The general formula is A₂M^IM^IIIX₆ (A is a monovalent cation, M^I is a univalent metal, M^III is a trivalent metal, and X is a halide). In this structure, M^IX₆ and M^IIIX₆ octahedra were connected alternatively. Although it does not show high mobility, it has superior stability toward ambient environments and great potential [48].

Various structures, new elements, and different compositions are adopted to raise the performance and stability of perovskite TFT (Figure 2, Table 3). Still, tremendous novel ways are veiled. Although perovskite has rapidly grown over the last decade, stability and down-scaling have to be investigated further to apply them to commercial backplanes.

Figure 2. The field effect mobility trends of MHPs TFTs for different chemical compositions.

Table 3. Recent progress of MHPs TFTs.

Year	Materials	Geometry	Substrate	Source Drain	Insulator	μFE (cm^2/V^−1s^−1)	Ion/Ioff	Ref
2016	PEA2SnI4	TGTC	Si	Au/MoO3	NH3I-SAM	12	10^6	[49]
2017	MAPbI3	BGBC	Si	Au	HfO2	1.05	10^4	[50]
	CsPbBr3	TGBC	Glass	Au	PMMA	0.26	10^4	[51]
2018	MAPbI3	BGTC	Si	Au/MoOx	SiO2	7.47	10^5	[52]
	MAPbBr3	BGBC	Si	Au	SiO2	3.6	10^5	[53]
	MAPbI3-xClx	BGTC	Si	Au	SiO2	10	10^3–10^4	[49]
2019	MAPbI3	BGBC	Si	Cr/Au	SiO2	15	10^6	[54]
	PEA2SnI4	BGTC	Si	Al/MoOx	SiO2	50	10^6	[55]
	(PEA)2CsSn2I7	BGBC	Si	Cr/Au	SiO2	11.6		[56]
	CsPbI3 Nanowire	BGTC	Si	Ti/Au	SiO2	3.05	10^4–10^5	[57]
	CsPbBr3 Nanowire	BGTC	Si	Ti/Au	SiO2	2.17	10^4–10^5	[57]
	CsPbCl3 Nanowire	BGTC	Si	Ti/Au	SiO2	1.06	10^4–10^5	[57]
2020	MAPbI3	BGTC	Si	Au/MoO3	Al2O3	21.41	10^4	[58]
	CsPbBr3/MEH-PPV	BGBC	Si	Au/Al	SiO2	9	10^6	[59]
	PEA2SnI4	BGTC	Si	Au	SiO2	4.11	10^6	[60]
	RbCsFAMAPbI3	BGTC	Glass	Au/Cr	Cytop	0.5	10^3	[61]
2021	PEA2MA5Pb6I19	BGTC	Si	Au/MoO3	SiO2	3.9	10^4	[62]
	FASnI3	BGBC	Si	Au	SiO2	0.21	10^4	[63]
2022	CsSnI3	BGTC	Si	Au	SiO2	51.4	3 × 10^8	[64]
	MASn(IxClyBr1-x-y)3	BGTC	Si	Au	HfO2	19.6	10^7	[46]
	MASn(IxCl1-x)3	BGTC	Si	Au	HfO2	9.5	10^7	[46]
	MASn(IxBr1-x)3	BGTC	Si	Au	HfO2	4.3	10^6	[46]
	MASnI3	BGTC	Si	Au	HfO2	1.3	10^6	[46]
	5 mol% SnI4 doped PEA2SnI4	BGBC	Si	Au	SiO2	0.68	10^5	[65]
	Cs2AgBiBr6	BGBC	Si	Au	SiO2	0.29	–	[48]

4. 2d transition metal dichalcogenides TFTs

2D transition metal dichalcogenides (TMDCs) have high ${\mu }_{FE}$, high mechanical flexibility, and layer-dependent band structure that differs from their bulk counterparts. Researchers have studied these unique material properties for decades [66,67], making TMDCs a candidate for next-generation materials in various fields, including backplane transistors for display. MoS₂ has attracted attention because it is readily available, and high-quality crystals can be easily obtained. MoS₂ is also mechanically and chemically robust [68]. However, TMDCs face difficulties in application due to factors such as high contact resistance (R_c), high subthreshold swing (SS), and I_on/I_off ratio. In particular, contact resistance has a dominant impact on the performance of FET devices, and solving this is the most important area of research in TMDCs.

Various strategies have been adopted in the 2D TMDCs field to reduce contact resistance, including molecular doping [69,70], phase engineering [71], graphene contact [72,73], edge contact [74,75], van der Waals contact [76,77], and semimetal interlayer contact [78,79]. Molecular doping is a simple and easily scalable method that has been extensively researched. Recently, thiol-based molecules have been found to provide the new tunneling path at the metal–semiconductor (MS) junction. This new tunneling path has lower energy barriers and exhibits Ohmic-contact behaviors, reducing R_c (to 25.2 kΩ·μm) [69].

Additionally, by forming a junction between the edge of the TMDC material and the metal, the issue of reduced contact length (L_c) in conventional devices has been solved. This device geometry ensures that the area of injection at the edge is no longer dependent on the physical contact length, improving the performance and R_c of FET devices (20.5 kΩ·μm) [75].

When forming MS junctions, physical and chemical damage can lead to difficulties achieving ohmic contacts, resulting in Fermi-level pinning, threshold-voltage variation, and unintentional doping [87,88]. Therefore, alternative methods to doping and edge contacts have been studied to avoid damage. Some platforms have been proposed to create MS-junctions in ultra-high vacuum to minimize contamination, and 2D materials like graphene have been used as electrodes to maximize the benefits of a dangling bond-free surface. [72,80] Additionally, the use of the transfer metal method instead of aggressive thermal evaporation using metal electrodes [76,80] and indium/gold electrodes [77] has been proposed as it results in ultraclean, stable, and damage-free van der Waals contact.

Traditionally, the gap state between MS junctions was thought to be caused by defects. However, in addition to defects, the Metal Induced Gap State (MIGS), which results from the hybridization of metal and semiconductor orbitals, can cause Fermi-level pinning [81–84]. Therefore, even with forming a defect-free interface using vdW contact, it was impossible to lower R_c below 1 kΩ·μm. Shen et al. focused on MIGS and used a semimetal with zero density of states near the fermi level as an interlayer to eliminate the Schottky barrier and demonstrate an ohmic contact MoS₂ FET. Most semimetals were effective, but bismuth (Bi), particularly, had a well-aligned conduction band and energy with MoS₂, achieving a much lower R_c than 1 kΩ·μm (0.123 kΩ·μm) [78].

In the past few decades, there has been rapid development in 2D TMDCs TFTs (Table 4, Figure 3. [a]) [44,45,47,69,72,74–80,85,86]. The R_c significantly affects TFTs’ performance and is essential for applying TMDCs. However, as seen in Figure 3. (b), most of the research on R_c improvement has focused on MoS2-based n-type transistors, and the world record is also based on n-type devices.

Figure 3. Contact resistance trends of 2D TMDCs based on (a) contact strategy, and (b) type of transistor.

Table 4. Recent progress of TMDCs TFTs.

	Channel	Deposition			S.S.	Ion/Ioff	Rc	Ion
Year	materials (thickness)	method	Strategy	${\mu }_{FE}$ (cm^2/Vs)	(V/dec)	Ion/Ioff	(kΩ·μm)	(μA/μm)	Ref
2016	MoS2(2-3L)	Mechanical exfoliation	Au UHV	20 (electrons)	–	–	2	75	[44]
2017	MoS2(3L)	CVD	-	-	–	–	2.9	0.8	[49]
2018	MoS2(4-20 nm)	Mechanical exfoliation	Transferring metal film	260 (electrons) 175 (holes)		10^6 10^6	-	∼ 660 ∼ 210	[49]
	MoS2(20 nm)	Mechanical exfoliation	Molecular doping	-	–	–	25.2	50	[49]
2019	MoS2(3L)	CVD	Edge contact	-	–	–	205	0.8	[49]
	MoS2(1L)	CVD	Graphene/Ag contact	35 (electrons)	–	∼ 10^8	115	-	[49]
	WSe2(2L)	Mechanical exfoliation	Transferred via contact	160 (holes)	0.064	10^6	3.5	∼ 50	[49]
	MoS2(1L)	Mechanical exfoliation	van der Waals In/Au contact	167 (electrons)	–	10^6	0.8	196	[49]
2021	MoS2(1L)	CVD	–	26 (electrons)	0.335	10^7	9.2	54	[49]
	WS2(1L)	CVD		33 (electrons)	0.443	10^7	29.2	13
	MoS2(1L)	CVD	Bi/Au contact	21 (electrons)	–	10^8	0.123	∼ 1000	[49]
	WSe2(1L)	CVD		17 (holes)		10^8	100 -1000	∼ 300
2023	MoS2(1L)	CVD	Sb/Au contact	∼70 (electrons)	∼ 0.250	∼ 10^8	0.209	∼550	[49]

A complete understanding of the causes and effects of contact resistance is necessary to improve TMDCs R_c. This understanding should be accompanied by research on n-type and p-type devices. Currently, the reason for the higher contact resistance of p-type TMD transistors compared to n-type TMD transistors is unclear, and further research is needed to understand the underlying cause. Furthermore, methods for creating large-area 2D materials for backplane TFTs in the display should be proposed. Most of the research on TMDCs is based on mechanical exfoliation, which is impractical for applications. Therefore, wafer-scale growth methods and solution-based exfoliation and film fabrication methods should be pursued together for large-area electronic applications.

5. Conclusions and perspectives

This paper comprehensively reviews recent progress and current research on TFTs based on metal oxides, metal–halide perovskites, and 2D TMDCs. While LTPS has been widely used in the industry, its high-production cost, limited compatibility with next-generation flexible displays, and high-temperature process have motivated the search for new materials. Materials with high flexibility, low-process temperature, and large-scale production and patterning capability are essential in applying flexible plastic substrates. Thus, the emerging materials should possess excellent material properties and be evaluated based on their fabrication to guide future research on TFTs for display.

Acknowledgments

Gwon Byeon, Seong Cheol Jang, and Taewan Roh contributed equally to this work. This study was supported by the Ministry of Science and ICT through the National Research Foundation, funded by the Korean Government (NRF-2021R1A2C3005401).

Disclosure statement

No potential conflict of interest was reported by the author(s).

Additional information

Funding

This work was supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (Grant number: 2021M3F3A2A03017873, 2021R1A6A1A03043682, 2022R1A2C2008273).

Notes on contributors

Gwon Byeon

Gwon Byeon received his B.S. degree in Chemical Engineering from the Pohang University of Science and Technology (POSTECH), Korea, in 2021. He is currently a Ph.D. student in the Department of Chemical Engineering at POSTECH under the supervision of Prof. Yong-Young Noh. His research interests include solution-processed 2D semiconducting materials for thin-film transistors.

Seong Cheol Jang

Seong Cheol Jang received his B.S. and M.S. degrees (2021) at the Department of Material Science and Engineering of Chungnam National University (CNU), Republic of Korea. He is currently working toward A doctoral degree at CNU. He has been researching oxide/nitride semiconductors, thin-film transistors (TFTs), polymer gate dielectrics, and flexible/stretchable devices.

Taewan Roh

Taewan Roh received his B.S. degree in Chemical Engineering from the Pohang University of Science and Technology (POSTECH) in 2021. He is currently a Ph.D. candidate in the Department of Chemical Engineering at POSTECH under the supervision of Prof. Yong-Young Noh. His research interests include the development of perovskite-based semiconductors through solution-process and thermal deposition, as well as their applications in transistors and circuits.

Ji-Min Park

Ji-Min Park is currently a Ph.D. student in the Department of Materials Science and Engineering in Chungnam National University (CNU), supervised by Prof. Hyun-Suk Kim. Her research interests include oxide/nitride semiconductors, bipolar semiconductors, thin-film transistors (TFTs), and neuromorphic devices.

Hyun-Suk Kim

Hyun-Suk Kim received his Ph.D. from the Korea Advanced Institute of Science and Technology (KAIST), Korea, in 2006. After completing a postdoctoral fellowship at MIT, USA from 2007 to 2009, he joined the Samsung Advanced Institute of Technology as a research staff member of the Display Devices Lab. In 2014, he moved to Chungnam National University, Republic of Korea as assistant professor. He is currently a professor in the Department of Materials Science and Engineering, Chungnam National University. His current research interests are thin film transistor, MOSFET, CMOS devices, all-solid-state-battery, materials design & modeling, thin film coating technologies, and surface & interface analyses.

Yong-Young Noh

Yong-Young Noh is Chair Professor of the Department of Chemical Engineering of Pohang University of Science and Technology (POSTECH). He received his Ph.D. degree in 2005 from GIST and then worked as a postdoctoral associate at the Cavendish Laboratory in Cambridge, UK. Afterward, he worked as a senior researcher at ETRI, as assistant professor at Hanbat National University, and as an associate professor at Dongguk University. His research interest is in developing printable semiconductors, including 2D materials, organic, carbon nanotubes, perovskite, metal halide, and metal oxide for field-effect transistors, photodetectors, and light-emitting diodes.