Modelling and performance evaluation of a novel internal-priority routing scheme for finite-buffered multistage interconnection networks

Abstract

In this paper, the modelling, analysis and performance evaluation of a novel architecture for internal-priority finite-buffered multistage interconnection networks (MINs) are presented. We model the proposed architecture giving the details of its operation and describing its states and detailing conditions and effects of state transition; we also provide a formal model for evaluating its performance. The proposed architecture's performance is subsequently analysed under the uniform traffic condition, considering various offered loads, buffer lengths and MIN sizes, using simulations. We compare the internal-priority scheme vs. the non-priority (or single priority) scheme, by gathering metrics for the two most important network performance factors, namely, packet throughput and the mean time a packet needs to traverse the network. We demonstrate and quantify the improvements on MIN performance stemming from the introduction of priorities in terms of throughput and a combined performance indicator which depicts the overall performance of the MIN. These performance measures can be valuable assets for designers of parallel multiprocessor systems and networks in order to minimise the overall deployment costs and delivering efficient systems.

Keywords:

• multistage interconnection networks
• Banyan switches
• packet switching
• performance analysis
• simulation model