Prediction of highly imbalanced semiconductor chip-level defects using uncertainty-based adaptive margin learning

Abstract

In semiconductor manufacturing, the package test is a process that verifies whether the product specifications are satisfied before the semiconductor products are finally shipped to customers. The packaged chips are classified as good or defective according to the verification results. To ensure high-quality products and customer satisfaction, it is important to detect defective chips during the package test. In this article, we consider the problem of predicting potential defects in advance using the wafer-test results data obtained from an earlier stage of the wafer test. There are several challenges in this problem. First, package-test data are highly class-imbalanced with a very low defect rate, and the imbalance level may vary due to the variability in manufacturing processes. Second, there is a complex relationship between package- and wafer-test results. Third, it is more important to increase the detection accuracy of defects than the overall classification accuracy. To address these challenges, we propose a Bayesian-neural-network-based prediction model. The proposed model adaptively considers unknown imbalance levels through the flexible adjustment of the decision boundary by using class- and sample-level prediction uncertainties and the relative frequency of each class. Using a real semiconductor manufacturing dataset from a global semiconductor company, we demonstrate that the proposed model can effectively predict defects even when the imbalance level of the test dataset differs from that of the training dataset.

Keywords:

• Bayesian neural network
• classification
• imbalance learning
• large margin softmax
• uncertainty

Acknowledgments

The authors would like to thank the referees, the associate editor, and the editor for reviewing this article and providing valuable comments.

Data availability statement

The data are not publicly available due to confidentiality.

Additional information

Funding

This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (2018R1C1B6004511, 2020R1A4A10187747).

Notes on contributors

Sumin Park

Sumin Park is a section manager in the Department of Mobile Test Engineering at SK hynix. He received his MS degree in industrial and systems engineering from KAIST and a BS degree in information and communication engineering from Chosun National University in Korea. His research interests are in the areas of applied statistics and data mining to predict failure and improve semiconductor processes.

Keunseo Kim

Keunseo Kim received a BS and MS degree in industrial and system engineering from KAIST. He is currently a PhD candidate in industrial and system engineering at KAIST. His research interests include Bayesian deep learning models and anomaly detection methods.

Heeyoung Kim

Heeyoung Kim received a BS degree in industrial engineering from KAIST, an M.S. degree in statistics and an M.S. degree in industrial engineering from the Georgia Institute of Technology and KAIST, respectively, and a PhD degree in industrial engineering from the Georgia Institute of Technology. She is an associate professor with the Department of Industrial and Systems Engineering, KAIST. She was a Senior Member of Technical Staff with AT&T Laboratories. Her research interests include applied statistics and machine learning.