A low power multisymbol CAVLC decoder for H.264/AVC

Abstract

A low power multisymbol structure of CAVLC decoder customised for H.264/AVC baseline profile is presented. The dependency property of CAVLC algorithm limits the usage of parallelism and pipelining techniques, but other techniques such as table partitioning and multisymbol are adopted to decrease power and increase throughput. A top-level CAVLC architecture is proposed first and then its subdecoders are designed and analysed. Finally, the proposed CAVLC decoder is implemented in 0·18 μm CMOS technology. The estimated area and power consumption are 14873 gates and 14·46 mW, respectively. The critical delay time is 5·59 ns when the decoder is operating at 167 MHz. The proposed low power multisymbol CAVLC decoder can be suitably applied in H.264/AVC decoding systems.

Keywords:

• CAVLC
• table partitioning
• multisymbol
• VLSI