Pareto optimal mapping for tile-based network-on-chip under reliability constraints

References

• D. Bertozzi, A. Jalabert, S. Murali, R. Tamhankar, S. Stergiou, L. Benini, and G. De Micheli, NoC synthesis flow for customized domain specific multiprocessor systems-on-chip, IEEE Trans. Parallel Distrib. Syst. 16 (2005), pp. 113–129. doi: 10.1109/TPDS.2005.22
   Web of Science ®Google Scholar
• P. Bogdan and R. Marculescu, A Theoretical Framework for On-Chip Stochastic Communication Analysis, 1st International Conference on Nano-Networks and Workshops, Lausanne, Switzerland, 2006.
   Google Scholar
• P. Bogdan, T. Dumitraş, and R. Marculescu, Stochastic communication: A new paradigm for fault-tolerant networks-on-chip, VLSI Design 2007 (2007), pp. 1–17. doi: 10.1155/2007/95348
   Google Scholar
• E.L.D.S. Carvalho, N.L.V. Calazans, and F.G. Moraes, Dynamic task mapping for MPSoCs, IEEE Design Test Comput. 27 (2010), pp. 26–35. doi: 10.1109/MDT.2010.106
   Web of Science ®Google Scholar
• C. Chen, Y. Lu, and S.D. Cotofana, A Novel Flit Serialization Strategy to Utilize Partially Faulty Links in Networks-On-Chip, Proceedings of the 2012 6th IEEE/ACM International Symposium on Networks-on-Chip, Copenhagen, Denmark, 2012, pp. 124–131.
   Google Scholar
• C-L. Chou and R. Marculescu, Contention-Aware Application Mapping for Network-On-Chip Communication Architectures, 26th IEEE International Conference on Computer Design, Lake Tahoe, USA, 2008, pp. 164–169.
   Google Scholar
• N. Choudhary, M.S. Gaur, V. Laxmi, and V. Singh, GA Based Congestion Aware Topology Generation for Application Specific NoC, 6th IEEE International Symposium on Electronic Design, Test and Application, Queenstown, New Zealand, 2011, pp. 93–98.
   Google Scholar
• R. Das, S. Eachempati, A.K. Mishra, V. Narayanan, and C.R. Das, Design and Evaluation of a Hierarchical On-Chip Interconnect for Next-Generation CMPs, International Symposium on High-Performance Computer Architecture, Takamatsu, Japan, 2009, pp. 175–186.
   Google Scholar
• R.P. Dick, E3S (embedded system synthesis benchmarks suite). Available at http://ziyang.eecs.umich.edu/ dickrp/e3s/.
   Google Scholar
• C. Grecu, A. Ivanov, R. Saleh, E.S. Sogomonyan, and P.P. Pande, On-Line Fault Detection and Location for NoC Interconnects, 12th IEEE International On-Line Testing Symposium, Como, Italy, 2006, pp. 145–150.
   Google Scholar
• J. Hu and R. Marculescu, Energy-Aware Mapping for Tile-Based NoC Architectures under Performance Constraints, ASP-DAC 2003. Asia and South Pacific, Yokohama, Japan, 2003, pp. 233–239.
   Google Scholar
• R. Marculescu, U.Y. Ogras, L.-S. Peh, N.E. Jerger, and Y. Hoskote, Outstanding research problems in NoC design: System, microarchitecture, and circuit perspectives, IEEE Trans Computer-Aided Design Integr. Circuits Syst. 28 (2009), pp. 3–21. doi: 10.1109/TCAD.2008.2010691
   Web of Science ®Google Scholar
• S. Murali, D. Atienz, L. Benini, and G. De Michel, A Multi-Path Routing Strategy with Guaranteed in-order Packet Delivery and Fault-Tolerance for Networks on Chip, Design Automation Conference, Piscataway, United States, 2006, pp. 845–848.
   Google Scholar
• N. Muralimanohar, R. Balasubramonian, and N. Jouppi, Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0, Annual International Symposium on Microarchitecture, Chicago, USA, 2007, pp. 3–14.
   Google Scholar
• B. Paul and M. Radu, Hitting time analysis for fault-tolerant communication at nanoscale in future multiprocessor platforms, IEEE Trans. Computer-Aided Design Integr. Circuits Syst. 30 (2011), pp. 1197–1210. doi: 10.1109/TCAD.2011.2138430
   Web of Science ®Google Scholar
• B. Paul and M. Radu, Non-stationary traffic analysis and its implications on multicore platform design, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Piscataway, USA, 2011, pp. 508–519.
   Google Scholar
• F. Refan, H. Alemzadeh, S. Safari, P. Prinetto, and Z. Navabi, Reliability in Application Specific Mesh-based NoC Architectures, 14th IEEE International On-Line Testing Symposium, Rhodes, Greece, 2008, pp. 207–212.
   Google Scholar
• P.K. Sahu, P. Venkatesh, S. Gollapalli, and S. Chattopadhyay, Application Mapping onto Mesh Structured Network-On-Chip Using Particle Swarm Optimization, IEEE Computer Society Annual Symposium on VLSI, Chennai, India, 2011, pp. 335–336.
   Google Scholar
• A. Sanusi and M.A. Bayoumi, Smart-Flooding: A Novel Scheme for Fault-Tolerant NoCs, International SOC Conference, Belfast, Ireland, 2009, pp. 259–262.
   Google Scholar
• V.N. Sastry, T.N. Janakiraman, and S. Ismail Mohideen, New Polynomial Time Algorithms to Compute a Set of Pareto Optimal Paths for Multi-Objective Shortest Path Problems, Int. J. Comput. Math. 82 (2005), pp. 289–300. doi: 10.1080/00207160412331296715
   Web of Science ®Google Scholar
• M.J. Sepulveda, M. Strum, and W.J. Chau, A Multi-Objective Adaptive Immune Algorithm for NoC Mapping, IFIP International Conference on Very Large Scale Integration, Florianopolis, Brazil, 2011, pp. 193–196.
   Google Scholar
• M.V.C.d. Silva, N. Nedjah, and L.M. Mourelle, Power-aware multi-objectives evolutionary optimization for application mapping on NoC platforms, Int. J. Electron. 97 (2010), pp. 1163–1179. doi: 10.1080/00207217.2010.512105
   Web of Science ®Google Scholar
• W. Song, D. Edwards, J.L. Nunez-Yanez, and S. Dasgupta, Adaptive Stochastic Routing in Fault-Tolerant On-Chip Networks, 3rd ACM/IEEE International Symposium on Networks-on-Chip, San Diego, USA, 2009, pp. 32–37.
   Google Scholar
• J. Sun, J. Liu, and W. Xu, Using quantum-behaved particle swarm optimization algorithm to solve non-linear programming problems, Int. J. Comput. Math. 84 (2007), pp. 261–272. doi: 10.1080/00207160601170254
   Web of Science ®Google Scholar
• T. Lei and S. Kumar, A Two-Step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture, Euromicro Symposium on Digital System Design, Belek Antalya, urkey, 2003, pp. 180–187.
   Google Scholar
• F. Van Den Bergh and A.P. Engelbrecht, A study of particle swarm optimization particle trajectories, Inf. Sci. 176 (2006), pp. 937–971. doi: 10.1016/j.ins.2005.02.003
   Web of Science ®Google Scholar
• J.-B. Wang, M. Chen, X. Wan, and C. Wei, Ant-colony-optimization-based scheduling algorithm for uplink CDMA nonreal-time data, IEEE Trans. Veh. Technol. 58 (2009), pp. 231–241. doi: 10.1109/TVT.2008.924983
   Web of Science ®Google Scholar
• J-B. Wang, Y. Jiao, X. Song, and M. Chen, Optimal training sequences for indoor wireless optical communications, J. Optics 14 (2012).
   Web of Science ®Google Scholar
• J-B. Wang, X-X. Xie, Y. Jiao, X. Song, X. Zhao, M. Gu, and M. Sheng, Optimal odd-periodic complementary sequences for diffuse wireless optical communications, Optical Eng. 51 (2012), 1–6, Article ID: 015401.
   Google Scholar
• L. Weichen, G. Zonghua, X. Jiang, W. Xiaowen, and Y. Yaoyao, Satisfiability modulo graph theory for task mapping and scheduling on multiprocessor systems, IEEE Trans. Parallel Dist. Syst. 22 (2011), pp. 1382–1389. doi: 10.1109/TPDS.2010.204
   Web of Science ®Google Scholar
• W. Zhou, Y. Zhang, and Z. Mao, Pareto Based Multi-Objective Mapping IP Cores Onto NoC Architectures, IEEE Asia-Pacific Conference on Circuits and Systems, Singapore, 2006, pp. 331–334.
   Google Scholar
• H. Zimmer and A. Jantsch, Error-tolerant interconnect schemes, in Interconnect-Centric Design for Advanced SoC and NoC, J. Nurmi, J. Isoaho, H. Tenhunen, and A. Jantsch, eds., Springer, New York, 2006, pp. 155–176.
   Google Scholar