Integrated classifier simulator and neurochip VHDL implementation

O. B. Efremides Laboratory of Digital Systems, Section of Electronics and Information Systems Technology, Department of Electrical & Computer Engineering, School of Engineering Democritus University of Thrace, Thrace, Greece

M. P. Bekakos Laboratory of Digital Systems, Section of Electronics and Information Systems Technology, Department of Electrical & Computer Engineering, School of Engineering Democritus University of Thrace, Thrace, GreeceCorrespondence[email protected]

D. J. Evans Department of Computing, Faculty of Engineering & Computing, The Nottingham Trent University, Nottingham, UK

References

Kastania A. N. Bekakos M. P. Neurochip architectural design for pattern recognition and classification 6th International Conference on Applications of High Performance Computing in Engineering Hawaii (2000) pp. 259–270
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