A purely map procedure for two-level multiple-output logic minimization

References

• Muller , D. E. 1954 . Application of Boolean algebra to switching circuit design and to error detection.” . IRE Transactions on Electronic Computers , EC-3 : 6 – 12 .
   Google Scholar
• Bartee , T. C. 1961 . Computer design of multiple-output logical networks . IEEE Transactions on Electronic Computers , EC-10 : 21 – 30 .
   Google Scholar
• Hong , S. J. , Cain , R. G. and Ostapko , D. L. 1974 . MINI: a heuristic approach for logic minimization . IBM Journal of Research and Development , 18 : 443 – 458 .
   Web of Science ®Google Scholar
• Brayton , R. K. , Hachtel , G. D. , McMullen , C. and Sangiovanni-Vincentelli , A. 1984 . Minimization Algorithms for VLSI Synthesis , Boston, MA : Kluwer Academic .
   Google Scholar
• Dagenais , M. R. , Agrawal , V. K. and Rumin , N. C. 1986 . McBoole: a new procedure for exact logic minimization . IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems , CAD-5 : 229 – 238 .
   Google Scholar
• Roth , J. P. 1999 . Mathematical Design , New York : IEEE Press .
   Google Scholar
• Muroga , S. 1979 . Logic Design and Switching Theory , New York : John Wiley .
   Google Scholar
• Hill , F. J. and Peterson , G. R. 1981 . Introduction to Switching Theory and Logical Design, , 3rd edn , New York : John Wiley .
   Google Scholar
• McCluskey , E. J. 1986 . Logic Design Principles , Englewood Cliffs, NJ : Prentice-Hall .
   Google Scholar
• Douglas , L. and David , P. 1991 . Design of Logic Systems, , 2nd edn , London : Chapman & Hall .
   Google Scholar
• Hill , F. J. and Peterson , G. R. 1993 . Computer Aided Logical Design with Emphasis on VLSI, , 4th edn , New York : John Wiley .
   Google Scholar
• Unger , S. H. 1997 . The Essence of Logic Circuits, , 2nd edn , New York : IEEE Press .
   Google Scholar
• Wakerly , J. F. 2001 . Digital Design: Principles and Practice, , 3rd edn , Upper Saddle River, NJ : Prentice-Hall .
   Google Scholar
• Brown , S. and Vranesic , Z. 2003 . Fundamentals of Digital Logic with Verilog Design , New york : McGraw-Hill .
   Google Scholar
• Roth , C. H. Jr . 2004 . Fundamentals of Logic Design, , 5th edn , Belmomt, CA : Brooks/Cole-Thomson Learning .
   Google Scholar
• Kolman , B. , Busby , R. C. and Ross , S. C. 2000 . Discrete Mathematical Structures, , 4th edn , Upper Saddle River, NJ : Prentice-Hall .
   Google Scholar
• Rushdi , A. M. 1997 . “ Karnaugh map ” . In Encyclopedia of Mathematics, Supplement Volume I , Edited by: Hazewinkel , M. 327 – 328 . Dordrecht : Kluwer Academic . Available online at: http://eom.springer.de/K/k110040.htm(accessed 18 December 2006)
   Google Scholar
• Rushdi , A. M. 2001 . Using variable-entered Karnaugh maps to solve Boolean equations . International Journal of Computer Mathematics , 78 : 23 – 38 .
   Web of Science ®Google Scholar
• Rushdi , A. M. and Ba-Rukab , O. M. 2003 . Two-level multiple-output logic minimization using a single function . International Journal of Computer Mathematics , 80 : 979 – 985 .
   Google Scholar
• Brown , F. M. 2003 . Boolean Reasoning: The Logic of Boolean Equations, , 2nd edn , New York : Dover Publications .
   Google Scholar
• Rushdi , A. M. and Ba-Rukab , O. M. 2003 . Low-cost design of multiple-output switching circuits using map solutions of Boolean equations . Umm Al-Qura University Journal of Science–Medicine–Engineering , 15 ( 2 ) : 59 – 79 .
   Google Scholar
• Rushdi , A. M. and Ba-Rukab , O. M. A map procedure for two-level multiple-output logic minimization . Proceedings of the 17th National Computer Conference . Al-Madinah Al-Munw'warah, Saudi Arabia. pp. 517 – 528 .
   Google Scholar