Building a multi-FPGA-based emulation framework to support networks-on-chip design and verification

References

• Abdellah-Medjadji , K.-M. , Senouci , B. and Petrot , F. ‘Large Scale On-Chip Networks: An Accurate Multi-FPGA Emulation Platform’ . 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools . pp. 3 – 9 .
   Google Scholar
• Benini , L. and De Micheli , G. 2002 . ‘Networks On Chips: A New SoC Paradigm’ . Computer , 35 : 70 – 78 .
   Web of Science ®Google Scholar
• Bertozzi , D. , Jalabert , A. , Murali , S. , Tamhankar , R. , Stergiou , S. , Benini , L. and De Micheli , G. 2005 . ‘NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-On-Chip’ . IEEE Transactions on Parallel and Distributed Systems , 16 : 113 – 129 .
   Web of Science ®Google Scholar
• Chan , J. and Parameshwaran , S. ‘NoCGEN: A Template Based Reuse Methodology for Networks On Chip Architecture’ . 17th International Conference on VLSI Design . pp. 717 – 720 .
   Google Scholar
• Coppola , M. , Curaba , S. , Grammatikakis , M. D. , Locatelli , R. , Maruccia , G. and Papariello , F. 2004 . ‘OCCN: a NoC Modeling Framework for Design Exploration’ . Journal of Systems Architecture , 50 : 129 – 163 .
   Web of Science ®Google Scholar
• Dally , W. J. and Towles , B. ‘Route Packets, Not Wires: On-Chip Interconnection Networks’ . Proceedings of the 38th Design Automation Conference . pp. 684 – 689 .
   Google Scholar
• Genko , N. , Atienza , D. , De Micheli , G. and Benini , L. 2007 . ‘Feature-NoC Emulation: A tool and Design Flow for MPSoC’ . IEEE Circuits and Systems Magazine , 7 : 42 – 51 .
   Web of Science ®Google Scholar
• Jantsch , A. and Tenhunen , H. 2003 . Networks On Chip , New York : Springer .
   Google Scholar
• Kouadri-Mostefaoui , A. M. , Senouci , B. and Petrot , F. ‘Large Scale On-Chip Networks: An Accurate Multi-FPGA Emulation Platform’ . Proceedings of the 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools . pp. 3 – 9 .
   Google Scholar
• Krasteva , Y. E. , Criado , F. , Torre , E. and Riesgo , T. ‘A Fast Emulation-Based NoC Prototyping Framework’ . International Conference on Reconfigurable Computing and FPGAs . pp. 211 – 216 .
   Google Scholar
• Kumar , A. , Hansson , A. , Huisken , J. and Corporaal , H. ‘An FPGA Design Flow for Reconfigurable Network-Based Multi-Processor Systems On Chip’ . Design, Automation & Test in Europe Conference & Exhibition . pp. 1 – 6 .
   Google Scholar
• Lee , K. , Lee , S. J. and Yoo , H. J. 2006 . ‘Low-Power Network-On-Chip For High-Performance SoC Design’ . IEEE Transactions on Very Large Scale Integration (VLSI) Systems , 14 : 148 – 160 .
   Web of Science ®Google Scholar
• Liu , J. , Shen , M. , Zheng , L. R. and Tenhunen , H. ‘System Level Interconnect Design for Network-On-Chip Using Interconnect IPs’ . Proceedings of the 2003 International Workshop on System-Level Interconnect Prediction . pp. 117 – 124 .
   Google Scholar
• Liu , P. , Wang , W. , Xiao , Z. , Lai , L. , Teng , Z. , Yu , G. , Chen , K. , Jiang , Z. , Zhang , Y. , Zhou , J. , Cai , W. , Zhai , Z. , Shi , C. and Yao , Q. ‘MediaSOC: A System-On-Chip Architecture for Multimedia Application’ . IEEE International Workshop on VLSI Design and Video Technology . pp. 203 – 206 .
   Google Scholar
• Liu , P. , Xia , B. , Xiang , C. , Wang , X. , Wang , W. and Yao , Q. 2009a . ‘A Networks-On-Chip Architecture Design Space Exploration – The LIB’ . Computers and Electrical Engineering , 35 : 817 – 836 .
   Web of Science ®Google Scholar
• Liu , P. , Xiang , C. , Wang , X. , Xia , B. , Liu , Y. , Wang , W. and Yao , Q. ‘A NoC Emulation/Verification Framework’ . Sixth International Conference on Information Technology: New Generations . pp. 859 – 864 .
   Google Scholar
• Mahadevan , S. , Virk , K. and Madsen , J. 2007 . ‘ARTS: A SystemC-Based Framework For Multiprocessor Systems-On-Chip Modelling’ . Design Automation of Embedded Systems , 11 : 285 – 311 .
   Web of Science ®Google Scholar
• Marculescu , R. , Ogras , U. Y. , Peh , L. S. , Jerger , N. E. and Hoskote , Y. 2009 . ‘Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives’ . IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , 28 : 3 – 21 .
   Web of Science ®Google Scholar
• MIPS Corp . 2005 . ‘HMIPS32 Architecture for Programmers Volume II: The MIPS32 Instruction SetH’ http://www.mips.com/products/architectures/mips32/index.cfm#resources
   Google Scholar
• Moraes , F. , Calazans , N. , Mello , A. , Mller , L. and Ost , L. 2004 . ‘HERMES: An Infrastructure for Low Area Overhead Packet-Switching Networks On Chip’ . Integration, the VLSI Journal , 38 : 69 – 93 .
   Web of Science ®Google Scholar
• Ogras , U. Y. , Marculescu , R. , Lee , H. G. , Choudhary , P. , Marculescu , D. , Kaufman , M. and Nelson , P. 2007 . ‘Challenges and Promising Results in NoC Prototyping using FPGAs’ . IEEE Micro , 27 : 86 – 95 .
   Web of Science ®Google Scholar
• Xia , B. , Wu , K. , Xiang , C. , Yang , M. , Liu , P. and Yao , Q. 2010 . ‘Network Interface Design Based on Mutual Interface Definition’ . International Journal of High Performance Systems Architecture , 2 : 168 – 176 .
   Google Scholar
• Xilinx . 2008 . ‘Virtex-5 FPGA RocketIO GTX Transceiver User Guide’ http://www.xilinx.com/support/documentation/virtex-5.htm
   Google Scholar
• Xilinx Corp . 2008 . ‘Virtex-5 FPGA Configuration User Guide’ http://www.xilinx.com/support/documentation/virtex-5.htm
   Google Scholar
• Yang , G. , Yang , M. , Yang , Y. and Jiang , Y. ‘On the Implementation Physical Layout of PRDT-Based NoCs’ . International Conference on Information Technology . pp. 729 – 733 .
   Google Scholar