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Short Paper

High speed multiplier using Nikhilam Sutra algorithm of Vedic mathematics

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Pages 300-307 | Received 19 Sep 2011, Accepted 06 Jan 2013, Published online: 10 Apr 2013

References

  • Chidgupkar, P. D., & Karad, M. T. (2004). The implementation of vedic algorithms in digital signal processing. Global Journal of Engineering. Education, 8, 153–158.
  • Dhillon, H. S., & Mitra, A. (2008). A reduced-bit multiplication algorithm for digital arithmetic. International Journal of Computational and Mathematical Sciences, 2, 64–69. 
  • Maharaja, J. S. S. B. K. T. (2009). Vedic mathematics. Delhi: Motilal Banarsidass.
  • Mehta, P., & Gawali, D. (2009). Conventional versus vedic mathematical method for hardware implementation of a multiplier. In International conference on advances in computing, control, and telecommunication technologies (pp. 640–642). Trivandrum, Kerala, India.
  • Parhami, B. (2010). Computer arithmetic algorithms and hardware architectures (2nd ed). New York: Oxford University Press.
  • Pradhan, M., & Panda, R. (2010). Design and implementation of vedic multiplier. A.M.S.E. Journal, Series D, Computer Science and Statistics, France, 15(2), 1–19.
  • Pushpangadan, R., Sukumaran, V., Innocent, R., Sasikumar, D., & Sundar, V. (2009). High speed Vedic multiplier for digital signal processors. IETE Journal of Research, 55, 282–286.
  • Ramalatha, M., Deena Dayalan, K., Dharani, P., & Deborah Priya, S. (2009). High speed energy efficient ALU design using Vedic multiplication technique. ACTEA IEEE Zouk Mosbeh (pp. 600–603). Lebanon.

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