References
- Bay, H., Ess, A., Tuytelaars, T., & Van Gool, L. (2008). Speeded-up robust features (SURF). Computer Vision and Image Understanding, 110, 346–359.
- Bonato, V., Marques, E., & Constantinides, G. (2008). A parallel hardware architecture for scale and rotation invariant feature detection. IEEE Transactions on Circuits and Systems for Video Technology, 18, 1703–1712.
- Bouris, D., Nikitakis, A., & Papaefstathiou, I. (2010). Fast and efficient FPGA-based feature detection employing the SURF algorithm. In 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2010 (pp. 3–10). New York, NY: IEEE.
- Evans, C. (2009). Notes on the opensurf library (Tech. Rep. CSTR-09-001). Bristol: University of Bristol.
- Griffin, G., Holub, A., & Perona, P. (2007). Caltech-256 object category dataset. Pasadena, CA: California Institute of Technology.
- Lowe, D. (1999). Object recognition from local scale-invariant features. In The Proceedings of the Seventh IEEE International Conference on Computer Vision, 1999, Vol. 2 (pp. 1150–1157). New York, NY: IEEE.
- Mikolajczyk, K., & Schmid, C. (2005). A performance evaluation of local descriptors. IEEE Transactions on Pattern Analysis and Machine Intelligence, 27, 1615–1630.
- Schaeferling, M., & Kiefer, G. (2010). Flex-SURF: A flexible architecture for FPGA-based robust feature extraction for optical tracking systems. In International Conference on Recon-Figurable Computing and FPGAs (ReConFig), 2010 (pp. 458–463). New York, NY: IEEE.
- Schulz, A., Jung, F., Hartte, S., Trick, D., Wojek, C., Schindler, K., Ackermann, J., & Goesele, M. (2011). CUDA SURF-A real-time implementation for SURF. Retrieved from http://www.d2.mpi-inf.mpg.de/surf?q=surf
- Svab, J., Krajnik, T., Faigl, J., & Preucil, L. (2009). FPGA based speeded up robust features. In IEEE International Conference on Technologies for Practical Robot Applications, TePRA, 2009 (pp. 35–41). New York, NY: IEEE.
- Yao, L., Feng, H., Zhu, Y., Jiang, Z., Zhao, D., & Feng, W. (2009). An architecture of optimised SIFT feature detection for an FPGA implementation of an image matcher. In International Conference on Field-Programmable Technology, FPT, 2009 (pp. 30–37). New York, NY: IEEE.