A high-resolution time-to-digital converter using a three-level resolution

References

• Abadian, A., Lotfizad, M., Erfani-Majd, N., Ghaznavi-Ghoushchi, M.-B., & Mirzaie, H. (2010, December). A new low power and low-complexity all digital PLL (ADPLL) in 180nm and 32nm. In 17th IEEE international conference on electronics, circuits, and systems, Athens (pp. 305–310). IEEE.
   Google Scholar
• Andersson, N. U., & Vesterbacka, M. (2014). A vernier time-to-digital converter with delay latch chain architecture. IEEE Transactions on Circuits and Systems II: Express Briefs, 61(10), 773–777. doi:10.1109/TCSII.2014.2345289
   Web of Science ®Google Scholar
• Brok, V. D. (2012). Design and implementation of an Analog-to-Time-to-Digital converter ( M.Sc Thesis). University of Twente, Netherlands.
   Google Scholar
• Cheng, K.-H., Chang-Chien, H., Liu, J.-C., & Huang, H.-Y. (2010, April). A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop. In 13th IEEE international symposium on design and diagnostics of electronic circuits and systems, Vienna (pp. 285–288). IEEE.
   Google Scholar
• Choi, K.-C., Lee, S.-W., Lee, B.-C., & Choi, W.-Y. (2012). A time-to-digital converter based on a multiphase reference clock and a binary counter with a novel sampling error corrector. IEEE Transactions on Circuits and Systems II: Express Briefs, 59(3), 143–147. doi:10.1109/TCSII.2012.2184370
   Web of Science ®Google Scholar
• Chung, M. H., & Chou, H. P. (2011, October). A time-to-digital converter using vernier delay line with time amplification technique. In IEEE nuclear science symposium conference record, Valencia (pp. 772–775). IEEE.
   Google Scholar
• Hwang, C.-S., Chen, P., & Tsao, H.-W. (2004). A high-precision time-to-digital converter using a two-level conversion scheme. IEEE Transactions on Nuclear Science, 51(4), 1349–1352. doi:10.1109/TNS.2004.832902
   Web of Science ®Google Scholar
• Jovanović, G. S., & Stojčev, M. K. (2009). Vernier’s delay line time–to–digital converter. Scientific Publications of the State University of Novi Pazar, 1(1), 11–20.
   Google Scholar
• Kim, K. S., Kim, Y. H., Yu, W. S., & Cho, S. H. (2012, June). A 7b, 3.75ps resolution two-step time-to-digital converter in 65nm CMOS using pulse-train time amplifier. In Symposium on VLSI circuits digest of technical papers, Honolulu. IEEE.
   Google Scholar
• Kwang Seok, K., Won Sik, Y., & Seong Hwan, C. (2014). A 9 bit, 1.12 ps resolution 2.5 b/stage pipelined time-to-digital converter in 65 nm CMOS using time-register. IEEE Journal of Solid-State Circuits, 90(4), 1007–1016.
   Google Scholar
• Lee, M., & Abidi, A. A. (2007, June). A 9 b, 1.25 ps resolution coarse-fine time-to-digital converter in 90 nm CMOS that amplifies a time residue. In IEEE symposium on VLSI circuits, Kyoto (pp. 168–169). IEEE.
   Google Scholar
• Lee, M., Heidari, M. E., & Abidi, A. A. (2009). A low-noise wideband digital phase-locked loop based on a coarse–fine time-to-digital converter with subpicosecond resolution. IEEE Journal of Solid-State Circuits, 44(10), 2808–2816. doi:10.1109/JSSC.2009.2028753
   Web of Science ®Google Scholar
• Lu, P., & Andreani, P. (2010, November). A high-resolution vernier gated-ring-oscillator TDC in 90-nm CMOS. In IEEE conference NORCHIP, Tampere (pp. 1–4). IEEE.
   Google Scholar
• Mäntyniemi, A., Rahkonen, T., & Kostamovaara, J. (1997). A 9-channel integrated time-to-digital converter with sub-nanosecond resolution. Proceedings of the 40th Midwest Symposium on Circuits and Systems, 1, 189–192.
   Google Scholar
• Naraghi, S., Courcy, M., & Flynn, M. (2010). A 9-bit, 14 μw and 0.06 mm2 pulse position modulation ADC in 90-nm digital CMOS. IEEE Journal of Solid-State Circuits, 45(9), 1870–1880. doi:10.1109/JSSC.2010.2050945
   Web of Science ®Google Scholar
• Nose, K., Kanagawa, N. E. C., Kajita, M., & Mizuno, M. (2006, February). A 1ps-resolution jitter-measurement macro using interpolated jitter oversampling. IEEE international solid-state circuits conference, San francisco, CA (pp. 2112–2121). IEEE.
   Google Scholar
• Park, Y., & Wentzloff, D. (2011). A cyclic vernier TDC for ADPLLs synthesized from a standard cell library. IEEE Transactions on Circuits and Systems I: Regular Papers, 58(7), 1511–1517. doi:10.1109/TCSI.2011.2158490
   Web of Science ®Google Scholar
• Seo, Y.-H., Lee, S.-K., & Sim, J.-Y. (2011). A 1-GHz digital PLL with a 3-ps resolution floating-point-number TDC in a 0.18-μm CMOS. IEEE Transactions on Circuits and Systems II: Express Briefs, 58(2), 70–74. doi:10.1109/TCSII.2011.2106315
   Web of Science ®Google Scholar
• Straayer, M. Z., & Perrott, M. H. (2008, June). An efficient high-resolution 11-bit noise-shaping multipath gated ring oscillator TDC. In IEEE symposium on VLSI circuits, Honolulu (pp. 82–83). IEEE.
   Google Scholar
• Temporiti, E., Weltin-Wu, C., Baldi, D., Tonietto, R., & Svelto, F. (2009). A 3GHz fractional all-digital PLL with a 1.8 MHz bandwidth implementing spur reduction techniques. IEEE Journal of Solid-State Circuits, 44(3), 824–834. doi:10.1109/JSSC.2008.2012363
   Web of Science ®Google Scholar
• Vamvakos, S. D., Staszewski, R. B., Sheba, M., & Waheed, K. (2006, October). Noise analysis of time-to-digital converter in all-digital PLLs. In IEEE Dallas/CAS workshop on design, applications, integration and software, Richardson, TX (pp. 87–90). IEEE.
   Google Scholar
• Vercesi, L., Liscidini, A., & Castello, R. (2010). Two-dimensions vernier time-to-digital converter. IEEE Journal of Solid-State Circuits, 45(8), 1504–1512. doi:10.1109/JSSC.2010.2047435
   Web of Science ®Google Scholar
• Waheed, K., Sheba, M., Staszewski, R. B., Dulger, F., & Vamvakos, S. D. (2010, September). Spurious free time-to-digital conversion in an ADPLL using short dithering sequences. In Custom integrated circuits conference IEEE, San Jose, CA (pp. 1–4, 19–22). IEEE.
   Google Scholar
• Wang, C.-C., Huang, C.-C., & Tseng, S. (2008). A low-power ADPLL using feedback DCO quarterly disabled in time domain. Microelectronics Journal, 39(5), 832–840. doi:10.1016/j.mejo.2007.12.029
   Web of Science ®Google Scholar
• Watanabe, T., Makino, Y., Ohtsuka, Y., Akita, S., & Hattori, T. (1993). A CMOS time-to-digital converter LSI with half-nanosecond resolution using a ring gate delay line. IEICE Transactions on Electronics, E76-C(12), 1774–1779.
   Google Scholar
• Yu, J., Dai, F. F., & Jaeger, R. C. (2010). A 12-bit vernier ring time-to-digital converter in 0.13 µm CMOS technology. IEEE Journal of Solid-State Circuits, 45(4), 830–842. doi:10.1109/JSSC.2010.2040306
   Web of Science ®Google Scholar
• Zhao, L., & Kim, Y. (2009, August). A novel all-digital phase-locked loop with ultra fast frequency and phase acquisition. In 52nd IEEE international midwest symposium on circuits and systems, Cancun (pp. 487–490). IEEE.
   Google Scholar