Analytical threshold voltage and subthreshold swing model for TMG FinFET

References

• Bhattacharya, D., & Jha, N. K. (2014, September). FinFETs: From devices to architectures. Advanced Electronic Materials, 2014, 1–21.
   Google Scholar
• El Hamid, H. A., Roig Guitart, J., & Iniguez, B. (2007, June). Two-dimensional analytical threshold voltage and subthreshold swing models of undoped symmetric double-gate MOSFETs. IEEE Transactions on Electron Devices, 54(6), 1402–1408.
   Web of Science ®Google Scholar
• Frank, D. J., Dennard, R. H., Nowak, E., Solomon, P. M., Taur, Y., & Wong, H. S. P. (2001, March). Device scaling limits of Si MOSFETs and their application dependencies. Proceedings of the IEEE, 89(3), 259–288.
   Web of Science ®Google Scholar
• Goel, E., Kumar, S., Singh, K., Singh, B., Kumar, M., & Jit, S. (2016). 2-D analytical modeling of threshold voltage for graded-channel dual-material double-gate MOSFETs. IEEE Transactions on Electron Devices, 63(3), 966–973.
   Web of Science ®Google Scholar
• Hong, Y., Guo, Y., Yang, H., Yao, J., Zhang, J., & Ji, X. 2014. A novel bulk-FinFET with dual-material gate. 2014 12th IEEE international conference on solid-state and integrated circuit technology (ICSICT) (pp. 1–3). Guilin. doi: 10.1109/ICSICT.2014.7021393
   Google Scholar
• Hou, Y. T., Li, M. F., Low, T., & Kwong, D. L. (2004, Nov). Metal gate work function engineering on gate leakage of MOSFETs. IEEE Transactions on Electron Devices, 51(11), 1783–1789.
   Web of Science ®Google Scholar
• Kumar, M. J., & Chaudhry, A. (2004, April). Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs. IEEE Transactions on Electron Devices, 51(4), 569–574.
   Web of Science ®Google Scholar
• Kumar, P. R., & Mahapatra, S. (2010, Dec). Analytical modelling of quantum threshold voltage for triple gate MOSFET. Solid State Electronics, 54, 1586–1591.
   Web of Science ®Google Scholar
• Kumar, S., Goel, E., Singh, K., Singh, B., Singh, P. K., Baral, K., & Jit, S. (2017, March). 2-D analytical modeling of the electrical characteristics of dual-material double-gate TFETs with a SiO2/HfO2 stacked gate-oxide structure. IEEE Transactions on Electron Devices, 64(3), 960–968.
   Web of Science ®Google Scholar
• Li, C., Zhuang, Y., & Zhang, L. 2012. Simulation study on FinFET with tri-material gate. 2012 IEEE international conference on electron devices and solid state circuit (EDSSC) (pp. 1–3). Bangkok. doi: 10.1109/EDSSC.2012.6482802
   Google Scholar
• Liao, Y. B., Chiang, M. H., Lai, Y. S., & Hsu, W. C. (2014, April). Stack gate technique for dopingless Bulk FinFETs. IEEE Transactions on Electron Devices, 61(4), 963–968.
   Web of Science ®Google Scholar
• Lou, H., Zhang, L., Zhu, Y., Lin, X., Yang, S., He, J., & Chan, M. (2012, July). A junctionless nanowire transistor with a dual-material gate. IEEE Transactions on Electron Devices, 59(7), 1829–1836.
   Web of Science ®Google Scholar
• Mehrad, M., & Orouji, A. A. (2010, June). Partially cylindrical fin field-effect transistor: A novel device for nanoscale applications. IEEE Transactions on Device and Materials Reliability, 10(2), 271–275.
   Web of Science ®Google Scholar
• Narendar, V., & Mishra, R. A. (2015). Analytical modeling and simulation of multigate FinFET devices and the impact of high-k dielectrics on short channel effects (SCEs). Superlattices Microstruct, 85, 357–369.
   Web of Science ®Google Scholar
• Narendar, V., Rai, S., & Tiwari, S. (2016). A two-dimensional (2D) analytical surface potential and subthreshold current model for the underlap dual-material double-gate (DMDG) FinFET. Journal of Computational Electronics, 15, 1316–1325.
   Web of Science ®Google Scholar
• Naskar, S., & Sarkar, S. K. (2013, September). Quantum analytical model for inversion charge and threshold voltage of short-channel dual-material double-gate SON MOSFET. IEEE Transactions on Electron Devices, 60(9), 2734–2740.
   Web of Science ®Google Scholar
• Pal, A., & Sarkar, A. (2014). Analytical study of dual material surrounding gate MOSFET to suppress short-channel effects (SCEs). Engineering Science and Technology,An International Journal, 17, 205–212.
   Google Scholar
• Paul, B. C., Tu, R., Fujita, S., Okajima, M., Lee, T. H., & Nishi, Y. (2007, July). An analytical compact circuit model for nanowire FET. IEEE Transactions on Electron Devices, 54(7), 1637–1644.
   Web of Science ®Google Scholar
• Pei, G., Kedzierski, J., Oldiges, P., Ieong, M., & Kan, E.-C.-C. (2002, August). FinFET design considerations based on 3-D simulation and analytical modeling. IEEE Transactions on Electron Devices, 49(8), 1411–1419.
   Web of Science ®Google Scholar
• Razavi, P., & Orouji, A. A. 2008. Nanoscale triple material double gate (TM-DG) MOSFET for improving short channel effects. 2008 International conference on advances in electronics and micro-electronics (pp. 11–14). Valencia. doi: 10.1109/ENICS.2008.33
   Google Scholar
• Reddy, G. V., & Kumar, M. J. (2005, March). A new dual-material double-gate (DMDG) nanoscale SOI MOSFET-two-dimensional analytical modeling and simulation. IEEE Transactions on Nanotechnology, 4(2), 260–268.
   Web of Science ®Google Scholar
• Rios, R., Cappellani, A., Armstrong, M., Budrevich, A., Gomez, H., Pai, R., … Kuhn., K. (2011, Sept). Comparison of junctionless and conventional trigate transistors with Lg down to 26 nm. IEEE Electron Device Letters, 32(9), 1170–1172.
   Web of Science ®Google Scholar
• Ritzenthaler, R., Lime, F., Iniguez, B., Faynot, O., & Cristoloveanu, S. 2010. 3D analytical modelling of subthreshold characteristics in Pi-gate FinFET transistors. Solid-state device research conference (ESSDERC), 2010 proceedings of the European (pp. 448–451). no. contract 216171. doi: 10.1109/ESSDERC.2010.5618179
   Google Scholar
• Sachid, A. B., Chen, M. C., & Hu, C. (2017, April). Bulk FinFET with low- $\kappa $ spacers for continued scaling. IEEE Transactions on Electron Devices, 64(4), 1861–1864.
   Web of Science ®Google Scholar
• Saha, R., Baishya, S., & Bhowmick, B. (2017). 3D analytical modeling of surface potential, threshold voltage, and subthreshold swing in dual material gate (DMG) SOI FinFET. Journal Of Computational Electronics, 17, 153–162.
   Web of Science ®Google Scholar
• Saxena, M., Haldar, S., Gupta, M., & Gupta, R. S. (2002, Nov). Physics-based analytical modeling of potential and electrical field distribution in dual material gate (DMG)-MOSFET for improved hot electron effect and carrier transport efficiency. IEEE Transactions on Electron Devices, 49(11), 1928–1938.
   Web of Science ®Google Scholar
• Subramanian, V., Mercha, A., Parvais, B., Loo, J., Gustin, C., Dehan, M., … Decoutere, S. (2007). Impact of fin width on digital and analog performances of n-FinFETs. Solid-State Electronics, 51, 551–559.
   Web of Science ®Google Scholar
• TCAD Sentaurus User Guide. (2013). Mountain View, CA, USA: Synopsys Inc.
   Google Scholar
• Tiwari, P. K., Dubey, S., Singh, M., & Jit, S. (2010). A two-dimensional analytical model for threshold voltage of short-channel triple-material double gate (TM-DG) MOSFETs. Journal of Applied Physics, 108, 074508:1–8.
   Web of Science ®Google Scholar
• Tsormpatzoglou, A., Dimitriadis, C. A., Clerc, R., Pananakakis, G., & Ghibaudo, G. (2008a, Oct). Semianalytical modeling of short-channel effects in lightly doped silicon trigate MOSFETs. IEEE Transactions on Electron Devices, 55(10), 2623–2631.
   Web of Science ®Google Scholar
• Tsormpatzoglou, A., Dimitriadis, C. A., Clerc, R., Pananakakis, G., & Ghibaudo, G. (2008b, Sept). Threshold voltage model for short-channel undoped symmetrical double-gate MOSFETs. IEEE Transactions on Electron Devices, 55(9), 2512–2516.
   Web of Science ®Google Scholar
• Tsormpatzoglou, A., Dimitriadis, C. A., Clerc, R., Rafhay, Q., Pananakakis, G., & Ghibaudo, G. (2007, Aug). Semi-analytical modeling of short-channel effects in Si and Ge symmetrical double-gate MOSFETs. IEEE Transactions on Electron Devices, 54(8), 1943–1952.
   Web of Science ®Google Scholar
• Tsormpatzoglou, A., Tassis, D. H., Dimitriadis, C. A., Collaert, G. N., & Pananakakis, G. (2011, March). Analytical threshold voltage model for lightly doped short-channel tri-gate MOSFET. Solid State Electronics, 57, 31–34.
   Web of Science ®Google Scholar
• Visweswara Rao, S., Jit, S., & Tiwari, P. K. (2014). A Quasi-3D threshold voltage model for dual-metal quadruple-gate MOSFETs. Chinese Physics Letters, 31(12), 128502:1–3.
   Web of Science ®Google Scholar
• Yang, W., Yu, Z., & Tian, L. (2007, May). Scaling theory for FinFETs based on 3-D effects investigation. IEEE Transactions on Electron Devices, 54(5), 1140–1147.
   Web of Science ®Google Scholar
• Yeh, M.-S., Wu, Y.-C., Hung, M.-F., Liu, K.-C., Jhan, Y.-R., Chen, L.-C., & Chang, C.-Y. (2013, July). Fabrication, characterization and simulation of Ω-gate twin poly-Si FinFET nonvolatile memory. Nanoscale Research Letters, 8(1), 331.
   PubMed Web of Science ®Google Scholar
• Young, K. K. (1989, Feb). Short-channel effect in fully depleted SOI MOSFETs. IEEE Transactions on Electron Devices, 36, 399–402.
   Web of Science ®Google Scholar
• Yu B., Chang L., Ahmed S., Wang H., Bell S., Yang C.-Y., ... Kyser, D. (2002). FinFET Scaling to 10nm gate length. International Electron Devices Meeting, 251–254. doi:10.1109/IEDM.2002.1175825
   Google Scholar