Novel design of power-efficient quaternary logic gates using CNTFET

References

• Chauhan, A., Mahor, L., & Tiwari, P. (2020). Low power quaternary adder using CNFET. Proceedings of 2nd International Conference on VLSI Device, Circuit and System, VLSI DCS 2020, 18–19. https://doi.org/10.1109/VLSIDCS47293.2020.9179898
   Google Scholar
• Cini, U., & Morgül, A. (2011). A current-mode multi-valued adder circuit for multi-operand addition. International Journal of Electronics, 98(6), 735–751. https://doi.org/10.1080/00207217.2011.567039
   Web of Science ®Google Scholar
• Current, K. W. (1993). Current-mode CMOS quaternary threshold logic full adder circuit. International Journal of Electronics, 74(4), 587–591. https://doi.org/10.1080/00207219308925862
   Web of Science ®Google Scholar
• Current, K. W., & McDonald, C. L. (1997). An adiabatic quaternary logic circuit. International Journal of Electronics, 83(1), 55–59. https://doi.org/10.1080/002072197135643
   Web of Science ®Google Scholar
• Daraei, A., & Hosseini, S. A. (2019). Novel energy-efficient and high-noise margin quaternary circuits in nanoelectronics. AEU - International Journal of Electronics and Communications, 105, 145–162. https://doi.org/10.1016/j.aeue.2019.04.012
   Web of Science ®Google Scholar
• Deng, J., & Wong, H. S. P. (2007a). A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application - part I: Model of the intrinsic channel region. IEEE Transactions on Electron Devices, 54(12), 3186–3194. https://doi.org/10.1109/TED.2007.909030
   Web of Science ®Google Scholar
• Deng, J., & Wong, H. S. P. (2007b). A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application - part II: Full device model and circuit performance benchmarking. IEEE Transactions on Electron Devices, 54(12), 3195–3205. https://doi.org/10.1109/TED.2007.909043
   Web of Science ®Google Scholar
• Doostaregan, A., & Abrishamifar, A. (2019). A new method for design of CNFET-Based quaternary circuits. Circuits, Systems, and Signal Processing, 38(6), 2588–2606. https://doi.org/10.1007/s00034-018-0981-7
   Web of Science ®Google Scholar
• Doostaregan, A., & Abrishamifar, A. (2020a). Evaluating a methodology for designing CNFET-Based ternary circuits. Circuits, Systems, and Signal Processing, 39(10), 5039–5058. https://doi.org/10.1007/s00034-020-01400-2
   Web of Science ®Google Scholar
• Doostaregan, A., & Abrishamifar, A. (2020b). On the design of robust, low power with high noise immunity quaternary circuits. Microelectronics Journal, 102, 104774. https://doi.org/10.1016/j.mejo.2020.104774
   Web of Science ®Google Scholar
• Ebrahimi, S. A., Reshadinezhad, M. R., Bohlooli, A., & Shahsavari, M. (2016). Efficient CNTFET-based design of quaternary logic gates and arithmetic circuits. Microelectronics Journal, 53, 156–166. https://doi.org/10.1016/j.mejo.2016.04.016
   Web of Science ®Google Scholar
• Jain, A. K., ABD-EL-BARR, M. H., & Bolton, R. J. (1993). A new structure for CMOS realization of MVL functions. International Journal of Electronics, 74(2), 251–263. https://doi.org/10.1080/00207219308925832
   Web of Science ®Google Scholar
• Khosroshahi, N. A., Dehyadegari, M., & Razaghian, F. (2022). A high-efficiency Wallace tree based multi-trit multiplier in CNTFET technology. International Journal of Electronics, 0(0), 1–19. https://doi.org/10.1080/00207217.2022.2068665
   Web of Science ®Google Scholar
• Lin, S., Kim, Y. -B., & Lombardi, F. (2009). A novel CNTFET-based ternary logic gate design. 2009 52nd IEEE International Midwest Symposium on Circuits and Systems, 1, 435–438. https://doi.org/10.1109/MWSCAS.2009.5236063
   Google Scholar
• Lin, S., Kim, Y. B., & Lombardi, F. (2011). CNTFET-based design of ternary logic gates and arithmetic circuits. IEEE Transactions on Nanotechnology, 10(2), 217–225. https://doi.org/10.1109/TNANO.2009.2036845
   Web of Science ®Google Scholar
• Lin, A., Wan, G., Deng, J., & Wong, H. -S.P. (2009). A quick user guide on Stanford University carbon nanotube field effect transistors (CNFET) HSPICE model. v.2.2.1. Stanford University.
   Google Scholar
• Moaiyeri, M. H., Doostaregan, A., & Navi, K. (2011). Design of energy-efficient and robust ternary circuits for nanotechnology. IET Circuits, Devices & Systems, 5(4), 285–296. https://doi.org/10.1049/iet-cds.2010.0340
   Web of Science ®Google Scholar
• Moaiyeri, M. H., Navi, K., & Hashemipour, O. (2012). Design and evaluation of CNFET-based quaternary circuits. Circuits, Systems, and Signal Processing, 31(5), 1631–1652. https://doi.org/10.1007/s00034-012-9413-2
   Web of Science ®Google Scholar
• Moaiyeri, M. H., Rahi, A., Sharifi, F., & Navi, K. (2017). Design and evaluation of energy-efficient carbon nanotube FET-based quaternary minimum and maximum circuits. Journal of Applied Research and Technology, 15(3), 233–241. https://doi.org/10.1016/j.jart.2016.12.006
   Google Scholar
• Murotiya, S. L., & Gupta, A. (2014). Design of CNTFET-based 2-bit ternary ALU for nanoelectronics. International Journal of Electronics, 101(9), 1244–1257. https://doi.org/10.1080/00207217.2013.828191
   Web of Science ®Google Scholar
• Nepal, K. (2010). Dynamic circuits for ternary computation in carbon nanotube based field effect transistors. Proceedings of the 8th IEEE International NEWCAS Conference, NEWCAS2010, Vdd, 53–56. https://doi.org/10.1109/NEWCAS.2010.5603726
   Google Scholar
• Prasad, V., Banerjee, A., & Das, D. (2022). Design of ternary encoder and decoder using CNTFET. International Journal of Electronics, 109(1), 135–151. https://doi.org/10.1080/00207217.2021.1908620
   Web of Science ®Google Scholar
• Raychowdhury, A., & Roy, K. (2005). Carbon-nanotube-based voltage-mode multiple-valued logic design. IEEE Transactions on Nanotechnology, 4(2), 168–179. https://doi.org/10.1109/TNANO.2004.842068
   Web of Science ®Google Scholar
• Roosta, E., & Hosseini, S. A. (2019). A novel multiplexer-based quaternary full adder in nanoelectronics. Circuits, Systems, and Signal Processing, 38(9), 4056–4078. https://doi.org/10.1007/s00034-019-01039-8
   Web of Science ®Google Scholar
• Sandhie, Z. T., Patel, J. A., & Ahmed, F. U. (2021). Investigation of multiple-valued logic technologies for beyond-binary era. ACM Computing Surveys, 54(1), 1–30. https://doi.org/10.1145/3431230ACM
   Web of Science ®Google Scholar
• Sharifi, F., Moaiyeri, M. H., Navi, K., & Bagherzadeh, N. (2015). Quaternary full adder cells based on carbon nanotube FETs. Journal of Computational Electronics, 14(3), 762–772. https://doi.org/10.1007/s10825-015-0714-0
   Web of Science ®Google Scholar
• Sharifi, F., Moaiyeri, M. H., Navi, K., & Bagherzadeh, N. (2016). Ultra-low-power carbon nanotube FET-based quaternary logic gates. International Journal of Electronics, 103(9), 1524–1537. https://doi.org/10.1080/21681724.2016.1138506
   Web of Science ®Google Scholar
• Tabrizchi, S., Sharifi, F., Badawy, A. H., & Saifullah, Z. M. (2017). Enabling energy-efficient ternary logic gates using CNFETs. 2017 IEEE 17th International Conference on Nanotechnology, NANO 2017, 542–547. https://doi.org/10.1109/NANO.2017.8117467
   Google Scholar
• Takbiri, M., Faghih Mirzaee, R., & Navi, K. (2019). Analytical review of noise margin in MVL: Clarification of a deceptive matter. Circuits, Systems, and Signal Processing, 38(9), 4280–4301. https://doi.org/10.1007/s00034-019-01063-8
   Web of Science ®Google Scholar
• Vendra, S. K., Chrzanowska-Jeske, M., & Ashraf, R. (2017). Statistical evaluation of critical path delay in CNFET-based circuits in the presence of CNT fabrication imperfections. 2017 IEEE 17th International Conference on Nanotechnology, NANO 2017, 364–369. https://doi.org/10.1109/NANO.2017.8117285
   Google Scholar
• Vidhyadharan, A. S., & Vidhyadharan, S. (2022). Mux based ultra-low-power ternary adders and multiplier implemented with CNFET and 45 nm MOSFETs. International Journal of Electronics, 109(1), 58–82. https://doi.org/10.1080/00207217.2021.1908616
   Web of Science ®Google Scholar
• Watanabe, T., Matsumoto, M., & Li, T. (1987). New logical-sum and logical-product circuits using CMOS transistors and their applications to four-valued combinational circuits. International Journal of Electronics, 63(2), 215–227. https://doi.org/10.1080/00207218708939124
   Web of Science ®Google Scholar