Investigation of Adiabatic Logic in Nano-meter Technology

References

• Agarwal, A., Gupta, T. K., & Dadoria, A. K. (2016). Ultra low power adiabatic logic using diode connected DC biased PFAL logic. Advances in Electrical and Electronic Engineering, 14(2), 122–130. https://doi.org/10.15598/aeee.v15i1.1974
   Google Scholar
• Amraee, M., Farshidi, E., & Kosarian, A. (2022). Improved turn-on speed of low power loads in pulsed power supply scheme and high energy efficiency. Journal of Circuits, Systems and Computers, 32(8). https://doi.org/10.1142/S0218126623500937
   Google Scholar
• Amraee, M., & Habibi, M. (2022). Application of a sigma-delta modulator for adiabatic charging of an output stage capacitor. International Journal of Electronics, 109(8), 1645–1660. https://doi.org/10.1080/00207217.2021.1992676
   Google Scholar
• Anuar, N., Takahashi, Y., & Sekine, T. (2010). Two phase clocked adiabatic static CMOS logic and its logic family. Journal of Semiconductor Technology and Science, 10(1), 1–10. https://doi.org/10.5573/JSTS.2010.10.1.001
   Web of Science ®Google Scholar
• Bhaaskaran, V. K. 2011. Energy recovery performance of quasi-adiabatic techniques using lower technology nodes. Power Electronics(IICPE), India International Conference on Electronics, pp. 1–7.
   Google Scholar
• Bhaaskaran, V. S., & Raina, J. P. (2008). Differential cascode adiabatic logic structure for low power. Journal of Low Power Electronics, 4(2), 178–190. https://doi.org/10.1166/jolpe.2008.264
   Google Scholar
• Bhuvana, B. P., & Kanchana, V. S. (2019). Design and analysis of IPAL for ultra-low power CRC architecture for applications in IoT based systems. International Journal of Electronics and Communications, 108, 127–140. https://doi.org/10.1016/j.aeue.2019.06.012
   Google Scholar
• Blotti, A., & Saletti, R. (2004). Ultra low-power adiabatic technique semi-custom design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(11), 1248–1253. https://doi.org/10.1109/TVLSI.2004.836320
   Web of Science ®Google Scholar
• Chaudhuri, D., Nag, A., Bose, S., & Mitra, S. (2015). 2N2N2P-An efficient adiabatic logic for VLSI design. National Conference on Emerging Technology and Applied Sciences (NCETAS), 4(9), 1–5.
   Google Scholar
• Denker, J. S. 1994. A review of adiabatic computing. Low Power Electronics, IEEE Symposium, San Diego, CA, USA (pp. 94–97).
   Google Scholar
• Gonzalez, R., Gordon, B. M., & Horowitz, M. A. (1997). Supply and threshold voltage scaling for low power CMOS. IEEE Journal of Solid-State Circuits, 32(8), 1210–1216. https://doi.org/10.1109/4.604077
   Web of Science ®Google Scholar
• Hinman, R. T., and Schlecht, M. F. 1994. Power dissipation measurements on recovered energy logic. Proceedings of IEEE Symposium on the VLSI Techniques, Digest of Technical Papers, pp. 19–20
   Google Scholar
• Indermaur, T., and Horowitz, M. 1994. Evaluation of charge recovery techniques and adiabatic switching for low power CMOS design. Proceedings of IEEE Symposium on Low Power Electronics, San Diego, CA, USA (pp. 102–103).
   Google Scholar
• Kramer, A., Denker, J. S., Flower, B., and Moroney, J. 1995. 2nd order adiabatic computation with 2N-2P and 2N-2N2P logic techniques. Proceedings of the International Symposium on Low Power Design, pp. 191–196
   Google Scholar
• Landauer, R. (1961). Irreversibility and heat generation in the computing process. IBM Journal of Research and Development, 5(3), 183–191. https://doi.org/10.1147/rd.53.0183
   Web of Science ®Google Scholar
• Li, P., Guo, J., Lin, Z., Hu, S., Shi, C., & Tang, F. (2020). A low-reverse-recovery-charge superjunction MOSFET with P-base and N-pillar schottky contacts. IEEE Transactions on Electron Techniques, 67(4), 1693–1698. https://doi.org/10.1109/TED.2020.2974904
   Web of Science ®Google Scholar
• Moon, Y. and Jeong, D. K. 1995. Efficient charge recovery logic. Proceedings of Digest of Technical Papers, Symposium on VLSI Circuits, Kyoto, Japan (pp. 129–130).
   Google Scholar
• Okuma, Y., Takeuchi, N., Yamanashi, Y., & Yoshikawa, N. (2019). Design and demonstration of an adiabatic-quantum-flux-parametron field-programmable gate array using Josephson-CMOS hybrid memories. IEEE Transactions on Applied Superconductivity, 29(8), 1–6. https://doi.org/10.1109/TASC.2019.2938577
   Web of Science ®Google Scholar
• Pandey, A. K., Upadhyay, S., Gupta, T. K., & Verma, P. K. (2019). Low power, high speed and noise immune wide-OR footless domino technique using keeper controlled method. Analog Integrated Techniques and Signal Processing, 100(1), 79–91. https://doi.org/10.1007/s10470-018-1336-9
   Web of Science ®Google Scholar
• Roy, K., Mukhopadhyay, S., and Meimand, H. M. 2003. Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS techniques. Proceedings of the IEEE, pp. 305–327
   Google Scholar
• Sachin, M., Bartlett, V. A., & Izzet, K. (2019). Modelling simulation and verification of 4-phase adiabatic logic design: A VHDL-based approach integration. Integration the VLSI Journal, 67, 144–154. https://doi.org/10.1016/j.vlsi.2019.01.007
   Web of Science ®Google Scholar
• Sharma, M., Pandey, D., Palta, P., & Pandey, B. K. (2021). Design and power dissipation consideration of PFAL CMOS V/S conventional CMOS based 2:1 multiplexer and full adder. Journal of Silicon, Springer, 28, 4401–4410. https://doi.org/10.1007/s12633-021-01221-1#
   Google Scholar
• Shinghal, D., Saxena, A., & Noor, A. (2013). Adiabatic logic techniques: A retrospect. MIT International Journal of Electronics & Communication Engineering, 3(2), 108–114.
   Google Scholar
• Takahashi, K., & Mizunuma, M. (2000). Adiabatic dynamic CMOS logic technique. Electronics and Communications in Japan (Part II: Electronics), 83(5), 50–58. https://doi.org/10.1002/(SICI)1520-6432(200005)83:5<50:AID-ECJB6>3.0.CO;2-X
   Web of Science ®Google Scholar
• Upadhyay, S., Mishra, R. A., Nagaria, R. K., & Singh, S. P. (2013). DFAL: Diode free adiabatic logic techniques. ISRN Electronics, Hindawi Publishing Corporation, 2013, 1–12. Article ID 673601. https://doi.org/10.1155/2013/673601/
   Google Scholar
• Upadhyay, S., Mishra, R. A., Nagaria, R. K., Singh, S. P., & Shukla, A. (2013). Triangular power supply based adiabatic logic techniques. World Applied Sciences Journal (WASJ), IDOSI Publications, 24(4), 444–450. https://doi.org/10.1155/2013/673601
   Google Scholar
• Upadhyay, S., Nagaria, R. K., & Mishra, R. A. (2013). Low-power adiabatic computing with improved quasi static energy recovery logic. VLSI Design, Hindawi, 2013, 1–9. https://doi.org/10.1155/2013/726324
   Google Scholar
• Upadhyay, S., Pandey, A. K., & Kumar, S. (2020). Performance evaluation of low power adiabatic techniques. Test Engineering and Management, 82, 4132–4137.
   Google Scholar
• Zhang, Y., Ding, D., Pan, Z., Wang, P., & Yu, Q. (2018). An ultra-low power multiplier using multi-valued adiabatic logic in 65 nm CMOS process. Microelectronics Journal, 78, 26–34. https://doi.org/10.1016/j.mejo.2018.05.016
   Web of Science ®Google Scholar