References
- DuMouchel, W., and F. O’Brien. 1989. “Integrating a Robust Option into a Multiple Regression Computing Environment.” Computer Science and Statistics: Proceedings of the 21st Symposium on the Interface, American Statistical Association, Alexandria, VA.
- Felix, N., A. Gaber, V. Menon, P. Longo, S. Halle, C. Koay, and M. Colburn. 2011. “Overlay Improvement Roadmap: Strategies for Scanner Control and Product Disposition for 5 nm Overlay.” In Proceedings of SPIE: Metrology, Inspection, and Process Control for Microlithography XXV, edited by C. J. Raymond, Vol. 7971, 79711D-1–79711D-7. San Jose, CA: SPIE.
- Hodge, V., and J. Austin. 2004. “A Survey of Outlier Detection Methodologies.” Artificial Intelligence Review 22: 85–126.10.1023/B:AIRE.0000045502.10941.a9
- Ignizio, James P., and Tom M. Cavalier. 1994. Linear Programming, 292–300. Englewood Cliffs, NJ: Prentice Hall.
- Lin, Z. C., and W. J. Wu. 1998. “A Study of Improving Overlay Accuracy for a Stepper in IC Manufacture.” The International Journal of Advanced Manufacturing Technology 14: 835–847.10.1007/BF01350768
- Lin, Z. C., and W. J. Wu. 1999. “Multiple Linear Regression Analysis of the Overlay Accuracy Model.” IEEE Transactions on Semiconductor Manufacturing 12: 229–237.
- Miyashiro, R., and Y. Fukagawa. 2009. “Optimization of Alignment in Semiconductor Lithography Equipment.” Precision Engineering 33: 327–332.10.1016/j.precisioneng.2008.09.001
- Moon, J. 2012. “State of the Art Technologies and Future Perspective in Display Industry.” IEEE International Electron Devices Meeting, San Francisco, CA. 1.2.1–1.2.4.
- Nakajima, S., Y. Kanaya, M. Li, T. Sugihara, A. Sukegawa, and N. Magome. 2003. “Outlier Rejection with Mixture Models in Alignment.” In Proceedings of SPIE: Optical Microlithography XVI, edited by A. Yen, Vol. 5040, 1729–1741. Santa Clara, CA: SPIE.
- Robinson, J., O. Fujita, H. Kurita, P. Izikson, D. Klein, and I. Tarshish-Shapir. 2011. “Improved Overlay Control Using Robust Outlier Removal Methods.” In Proceedings of SPIE: Metrology, Inspection, and Process Control for Microlithography XXV, edited by C. J. Raymond, Vol. 7971, 79711G-1–79711G-10. San Jose, CA: SPIE.
- Rorabacher, D. 1991. “Statistical Treatment for Rejection of Deviant Values: Critical Values of Dixon Q Parameter and Related Subrange Ratios at the 95 Percent Confidence Level.” Analytical Chemistry 63 (2): 139–146.10.1021/ac00002a010
- Shin, J., S. Lee, J. Yeo, H. Kim, J. Lee, and W. Han. 2008. “Study of Machine to Machine Overlay Error for Sub-60-nm Memory Devices.” Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 26: 2337–2340.10.1116/1.2998727
- Shin, J., S. Nam, T. Kim, Y. Bae, and J. Lee. 2009. “Application Results Lot-to-lot High-order and per-shot Overlay Correction for Sub-60-nm Memory Device Fabrication.” Journal of Micro/Nanolithography, MEMS, and MOEMS 8. Art. Id: 033008.
- Street, J. O., R. J. Carroll, and D. Ruppert. 1988. “A Note on Computing Robust Regression Estimates via Iteratively Reweighted Least Squares.” The American Statistician 42: 152–154.
- Sukegawa, A., S. Wakamoto, S. Nakajima, M. Kawakubo, and N. Magome. 2006. “Overlay Improvement by Using New Framework of Grid Compensation for Matching.” In Proceedings of SPIE: Metrology, Inspection, and Process Control for Microlithography XX, edited by C. N. Archie, Vol. 6152, 61523A-1–61523A-10. San Jose, CA: SPIE.
- Taylor, J. 1997. An Introduction to Error Analysis, 166–168. Sausalito, CA: University Science Books.
- Ueno, A., K. Tsujita, H. Kurita, Y. Iwata, M. Ghinovker, E. Kassel, and M. Adel. 2004. “Novel at-design-rule via-to-metal Overlay Metrology for 193-nm Lithography.” IEEE Transactions on Semiconductor Manufacturing 17: 311–316.10.1109/TSM.2004.831926