Performance analysis of a separate address/data bus multiprocessor system

References

• Adams , T. and Zimmerman , R. “An Analysis of 8086 Instruction Set Usage in MS DOS Programs,” . Proc. Third Symposium on Architectural Support for Programming Language and Oper. Syst., . pp. 152 – 161 . Boston, MA
   Google Scholar
• Akella , J. and Siewiorek , D.P. “Modeling and Measurement of the Impact of Input/Output on System Performance,” . Proc. of the 18th Annu. Symp. Comput. Architecture, . pp. 390 – 399 . Toronto, Canada
   Google Scholar
• Amdahl , G.M. 1967 . “Validity of the Single Processor Approach to Archiving Large Scale Computing Capability,” . American Federation of Informance Processing Societies, , : 483 – 485 .
   Google Scholar
• Chiang , M.C. and Sohi , G.S. 1992 . “Evaluating Design Choices for Shared Bus Multiprocessors in a Throughput‐Oriented Environment,” . IEEE Transactions on Computers, , 14 ( 3 ) : 297 – 317 .
   Google Scholar
• Decegama , A.L. 1989 . The Technology of Parallel Processing‐Parallel Processing Architectures and VLSI Hardware, Volume I, , Englewood Cliffs, NJ : Prentice‐Hall International Editions .
   Google Scholar
• Denning , P.J. and Buzen , J.P. 1978 . “The Operational Analysis of Queueing Network Model,” . ACM Comput. Sureveys, , 10 : 25 – 261 .
   Google Scholar
• Eggers , S.J. and Katz , R.H. “A Characterization of Sharing in Parallel Programs and Its Applicability to Coherency Protocol Evaluation,” . Proc. of the 15th Annu. Symp. Comput. Architecture, . pp. 373 – 382 . Hawaii
   Google Scholar
• Ein‐Dor and Feldmesser , J. 1987 . “Attributes of the Performance of Central Processing Units: a Relative Performance Prediction Model,” . Communications of the ACM, , Apr : 308 – 317 .
   Google Scholar
• Hennessy , J.L. and Patterson , D.A. 1990 . Computer Architecture a Quantitative Approach, , San Mateo, Calif. : Morgan Kaufmann Publishers .
   Google Scholar
• Intel . July 1991 . “XA‐MP Architecture Specification Ver 3.0,” . July ,
   Google Scholar
• Jain , R. 1991 . The Art of Computer Systems Performance Analysis, , New York : John Wiley & Sons .
   Google Scholar
• Lee , C.S. and Parng , T.M. 1993 . “A Subsystem‐Oriented Performance Analysis Methodology for Shared‐Bus Multiprocessors,” . NTUEE Tech. Report ,
   Google Scholar
• Lee , C.S. , Parng , T.M. , Lee , J.C. , Tsai , C.N. , Farn , K.J. , Chang , L.C. and Chen , L.P. “Performance Modelling and Evaluation for the XMP Shared‐Bus Multiproccessor Architecture,” . IEEE Conf. on Parallel and Distributed Systems . Hsinchu, Taiwan.
   Google Scholar
• Leutenegger , S. and Vernon , M.K. “AMean‐Value Performance Analysis of a New Multiprocessor Architecture,” . in Proc. ACM SIGMETRICS Conf. Measurement and Modelling of Comput. Syst. Santa Fe, New Mexico.
   Google Scholar
• Przybylski , S.A. 1990 . Cache and Memory Hierarchy Design: A Performance‐Directed Approach, , San Mateo, Calif. : Morgan Kaufmann Publishers .
   Google Scholar
• Jan. 1991 . “ SES/Workbench User's Manual and Reference's Manual ” . Jan. ,
   Google Scholar
• Short , R.T. and Levy , H.M. “A Simulation of Two‐Level Caches,” . Proc. of the 15th Annu. Symp. Comput. Architecture, . pp. 81 – 88 . Hawaii
   Google Scholar
• Tsuei , T.F. and Vernon , M.K. 1992 . “A Multiprocessor Bus Design Model Validated by System Measurement,” . IEEE Transactions on Parallel and Distributed Systems, , 3 ( 6 ) Nov. : 712 – 727 .
   Google Scholar
• Vernon , M.K. , Lazowska , E.D. and Zahorjan , J. “An Accurate and Efficient Performance Analysis Technique for Multiprocessor Snooping Cache‐Consistency Protocols,” . Proc. of the 15th Annu. Symp. Comput. Architecture . pp. 308 – 315 . Hawaii
   Google Scholar
• Correspondence addressee
   Google Scholar