VHDL Modeling and FPGA based Implementation of a Memory Efficient Huffman Decoder

Mohd HasanDepartment of Electronics Engineering, Aligarh Muslim University, Aligarh202 002, India. email: [email protected]View further author information

Prabhat AroraDepartment of Electronics Engineering, Aligarh Muslim University, Aligarh202 002, India. email: [email protected]

Manish SinghalDepartment of Electronics Engineering, Aligarh Muslim University, Aligarh202 002, India. email: [email protected]

S A AbbasiDepartment of Electronics Engineering, Aligarh Muslim University, Aligarh202 002, India. email: [email protected]

REFERENCES

AK Jain, Image Data Compression: A Review, Proc IEEE, vol 69, no 3, pp 349–389, May 1981.
Web of Science ®Google Scholar
D A Huffman, A Method for the construction of Minimum Redundancy codes, Proc IRE, vol 40, no 10, pp 1098–1101, Sept 1952.
Google Scholar
R Hashemian, Memory efficient and High speed search Huffman coding, IEEE Transactions on Communications, vol 43, no 10, pp 2576–2581, Oct 1995.
Web of Science ®Google Scholar
R Hashemian, High speed search and memory efficient Huffman coding, Proc IEEE International Symposium on Circuits and Systems, May 3–6, 1993.
Google Scholar
Z Navabi, VHDL Analysis and Modeling of Digital Systems, McGraw Hill Inc, 1993.
Google Scholar
D L Perry, VHDL, McGraw Hill Inc., 1995.
Google Scholar

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