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Articles

Crosstalk Analysis of Current-Mode Signalling-Coupled RLC Interconnects Using FDTD Technique

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References

  • N. A. Kurd, S. Bhamidipati, C. Mozak, J. L. Miller, T. M. Wilson, M. Nemani, and M. Chowdhury, “Westmere: A family of 32 nm IA processors,” in Proceeding of the IEEE International Solid-State Circuits Conference, Francisco, CA, 2010, pp. 96–7.
  • H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Lebanon, IN: Addison-Wesley, 1990.
  • A. K. Goel, High Speed VLSI Interconnections, 2nd ed. Hoboken, NJ: Wiley Interscience, 2007.
  • J. Liu, and X. Lin, “Equalization in high-speed communication systems,” IEEE Circuits Syst. Mag., Vol. 4, no. 2, pp. 4–17, Sep. 2004.
  • H. Wang, and Y. Cheng, “Equalization techniques for high-speed serial interconnect transceivers,” in Proceeding of the IEEE International Conference Solid State Integrated Circuit Technology, Beijing, 2008, pp. 1589–92.
  • E. Mensink, D. Schinkel, E. A. M. Klumperink, E. V. Tuijl, and B. Nauta, “Optimal positions of twists in global on-chip differential interconnects,” IEEE Trans. Very Large Scale Integr. Syst., Vol. 15, no. 4, pp. 438–46, Apr. 2007.
  • B. Kim, and V. Stojanovic, “Equalized interconnect for on-chip networks: Modeling and optimization framework,” in Proceeding of the IEEE International Conference on Computer Aided Design, Picataway, NJ, 2007, pp. 552–9.
  • F. Yuan, CMOS Current Mode Circuits for Data Communication, New York, NY: Springer, 2007.
  • S. Palermo, “Invited tutorial: Channel equalization: Techniques for high-speed electrical links,” IEEE Workshop on Microelectronics and Electron Devices, Boise, ID, Apr. 2013.
  • W. K. Chen, The VLSI Handbook, Boca Raton, FL: CRC Press, 2007.
  • M. A. Elgamel, and M. A. Bayoumi, “Interconnect noise analysis and optimization in deep submicron technologies,” IEEE Circuits Syst. Mag., Vol. 3, no. 4, pp. 6–17, Feb. 2003.
  • E. Salman, and E. G. Friedman, High Performance Integrated Circuit Design, San Jose, CA: McGraw-Hill, 2012.
  • K. M. Mohsin, A. Srivastava, A. K. Sharma, and C. Mayberry, “A thermal model for carbon nanotube interconnects,” J. Nanomater., Vol. 3, pp. 229–41, Apr. 2013.
  • W. Zeng, D. Gang, Y. Yintang, and L. Jianwei, “Crosstalk noise voltage of coupling RC interconnects with temperature distribution,” Chin. J. Electron., Vol. 19, no. 1, pp. 43–7, Jan. 2010.
  • M. Takahashi, M. Hashimoto, and H. Onodera, “Crosstalk noise estimation for generic RC trees,” in Proceeding of the International Conference on Computer Design, Austin, TX, 2001, pp. 110–6.
  • V. S. Rao, P. Mandal, and S. Sachdev, “High-speed lowcurrent duobinary signaling over active terminated chip-to-chip interconnect,” in Proceeding of the IEEE Symposium on Very Large Scale Integration, Tampa, FL, 2009, pp. 73–8.
  • J. Chen, “Self-calibrating on-chip interconnects,” Ph.D. dissertation, Electrical Department, Stanford University, 2012.
  • R. Dhiman, and R. Chandel, “Crosstalk analysis of CMOS buffer driven interconnects for ultra-low power applications,” J. Comput. Electron., Vol. 13, no. 2, pp. 360–9, Jun. 2013.
  • Y. I. Ismail, and E. G. Friedman, “Effects of inductance on the propagation delay and repeater insertion in VLSI circuits,” IEEE Trans. Very Large Scale Integr. Syst., Vol. 8, no. 2, pp. 195–206, Apr. 2000.
  • A. Naeemi, J. A. Davis, and J. D. Meindl, “Analysis and optimization for coplanar RLC lines for GSI global interconnections,” IEEE Trans. Electron Devices, Vol. 51, no. 6, pp. 985–94, Jun. 2004.
  • R. Dhiman, and R. Chandel, Compact Models and Performance Investigations for Sub-Threshold Interconnects, New-Delhi: Springer, 2014.
  • R. Chandel, S. Sarkar, and R. P. Agarwal, “An analysis of interconnect delay minimization by low voltage repeater insertion,” Microelectron. J., Vol. 38, no. 45, pp. 649–55, Apr.–May 2007.
  • B. Young, Digital Signal Integrity, Upper Saddle River, NJ: Prentice Hall PTR, 2011.
  • J. N. Tripathi, R. K. Nagpal, and R. Malik, “Signal integrity and power integrity issues at system level,” IETE Tech. Rev., Vol. 29, no. 5, pp. 365–71, Sep. 2012.
  • M. Pawan Kumar, S. Murali, and K. Veezhinathan, “Network-on-chips on 3-D ICs: Past, present, and future,” IETE Tech. Rev., Vol. 29, no. 4, pp. 318–35, Jul. 2012.
  • B. K. Kaushik, S. Sarkar, R. P. Agarwal, and R. C. Joshi, “Crosstalk analysis of simultaneously switching interconnects,” Int. J. Electron., Vol. 96, no. 10, pp. 1095–114, Sep. 2009.
  • K. Agarwal, D. Sylvester, and D. Blaauw, “Modeling and analysis of crosstalk noise in coupled RLC interconnects,” IEEE Trans. Comput.-Aided Des., Vol. 25, no. 5, pp. 892–901, May 2006.
  • J. V. R. Ravindra, and M. B. Srinivas, “Modeling and analysis of crosstalk for distributed RLC interconnects using difference model approach,” in Proceedings of the 20th Annual Conference on Integrated Circuits and Systems Design, Rio de Janeiro, 2007, pp. 207–11.
  • B. Lee, et al., “Design optimization for minimal crosstalk in differential interconnect,” in Proceeding of the Designcon, 2012, pp. 1263–92.
  • I. Hatirnaz, and Y. Leblebici, “Modelling and implementation of twisted differential on-chip interconnects for crosstalk noise reduction,” in Proceeding of the IEEE International Symposium Circuits Systems, Vancouver, 2004, pp. 185–8.
  • M.Masoumi, N. Masoumi, and A. Javanpak, “A new and efficient approach for estimating the accurate time domain response of single and capacitive coupled distributed RC interconnects,” Microelectron. J., Vol. 40, no. 8, pp. 1212–24, Aug. 2009.
  • V. Ramesh Kumar, B. K. Kaushik, and A. Patnaik, “An accurate model for dynamic crosstalk analysis of CMOS gate driven on-chip interconnects using FDTD method,” Microelectronics J., Vol. 45, no. 4, pp. 441–8, Apr. 2014.
  • V. Maheshwari, S. K. Jha, K. Khare, R. Kar, and D. Mandal, “Accurate crosstalk analysis for RLCG on-chip VLSI global interconnects,” in Proceeding of the IEEE Conference Information & Communication Technologies, Jeju Island, 2013, pp. 281–6.
  • K. Banerjee, and A. Mehrotra, “Accurate analysis of on-chip inductance effects and implications for optimal repeater insertion and technology scaling,” in Proceeding of the IEEE Symposium Very Large Scale Integration Circuits, Kyoto, 2001, pp. 195–8.
  • J. A. Davis, and J. D. Meindl, “Compact distributed RLC models__Part II: Coupled line transient expressions and peak crosstalk in multilevel interconnect networks,” IEEE Trans. Electron Devices, Vol. 47, no. 11, pp. 2078–87, Nov. 2000.
  • X. C. Li, J. F. Mao, and M. Swaminathan, “Transient analysis of CMOS-gate-driven RLGC interconnects based on FDTD,” IEEE Trans. Comput.-Aided Des., Vol. 30, no. 4, pp. 574–83, Apr. 2011.
  • V. Ramesh Kumar, B. K. Kaushik, and A. Patnaik, “An accurate FDTD model for crosstalk analysis of CMOS-gate-driven coupled RLC interconnects,” IEEE Trans. Electromag. Compat., Vol. 56, no. 5, pp. 1185–93, Oct. 2014.
  • Y. Agrawal, R. Chandel, and R. Dhiman, “Design and analysis of efficient multilevel receiver for current mode interconnect system,” in Proceeding of the IEEE Students’ Conference Electrical Electronics and Computer Sciences, Bhopal, 2014, pp. 1–6.
  • R. Bashirullah, W. Liu, and R. K. Cavin, “Current-mode signaling in deep submicrometer global interconnects,” IEEE Trans. Very Large Scale Integr. Syst., Vol. 11, no. 3, pp. 406–17, Jun. 2003.
  • M. Dave, M. Jain, M. S. Baghini, and D. Sharma, “A variation tolerant current mode signaling scheme for on-chip interconnects,” IEEE Trans. Very Large Scale Integr. Syst., Vol. 21, no. 2, pp. 342–53, Feb. 2013.
  • A. Vittal, and M. Marek-Sadowska, “Crosstalk reduction for VLSI,” IEEE Trans. Comput.-Aided Des., Vol. 16, no. 3, pp. 290–8, Mar. 1997.
  • C. J. Alpert, A. Devgan, and C. V. Kashyap, “RC delay metrics for performance optimization,” IEEE Trans. Comput.-Aided Des., Vol. 20, no. 5, pp. 571–82, May 2001.
  • K. T. Tang, and E. G. Friedman, “Lumped verses distributed RC and RLC interconnect impedances,” in Proceeding of the IEEE Midwest Symposium Circuits Systems, Lansing, MI, 2000, pp. 136–9.
  • S. Y. Kim, “Modeling and screening on-chip interconnect inductance,” Ph.D. dissertation, Electrical Department, Standford University, 2004.
  • R. Gupta, and L. Pileggi, “Modeling lossy transmission lines using the method of characteristics,” IEEE Trans. Circuits Syst. I, Vol. 43, no. 7, pp. 580–2, Jul. 1996.
  • Q. Xu, Z. F. Li, J. Wang, and J. F. Mao, “Transient analysis of lossy interconnects by modified method of characteristics,” IEEE Trans. Circuits Syst. I, Vol. 47, no. 3, pp. 363–75, Mar. 2000.
  • J. E. Bracken, V. Raghavan, and R. A. Rohrer, “Interconnect simulation with asymptotic waveform evaluation (AWE),” IEEE Trans. Circuits Syst. I, Vol. 39, no. 11, pp. 869–78, Nov. 1992.
  • J. F. Mao, and Z. F. Li, “Analysis of the time response of non uniform multi conductor transmission line with a method of equivalent cascaded network chain,” IEEE Trans. Microw. Theory Tech., Vol. 40, no. 5, pp. 948–54, May 1992.
  • J. S. H. Wang, and W. W. M. Dai, “Optimal design of self-damped lossy transmission lines for multichip modules,” in Proceeding of the IEEE Conference Computer Design, Cambridge, MA, 1994, pp. 594–8.
  • R. Kar, K. R. Reddy, A. K. Mal, and A. K. Bhattacherjee, “An explicit approach for bandwidth evaluation of on-chip VLSI RC interconnects with current mode signaling technique,” in Proceeding of the IEEE International Conference Computing Communication and Networking Technologies, Karur, 2010, pp. 1–4.
  • M. Celik, L. Pileggi, and A. Odabasioglu, IC Interconnect Analysis, Dordrecht: Springer, 2002.
  • R. Achar, and M. S. Nakhla, “Simulation of high speed interconnects,” Proc. IEEE, Vol. 89, no. 5, pp. 693–728, May 2001.
  • C. R. Paul, “Incorporation of terminal constraints in the FDTD analysis of transmission lines,” IEEE Trans. Electromag. Compat., Vol. 36, no. 2, pp. 85–91, May 1994.
  • J. A. Roden, C. R. Paul, W. T. Smith, and S. D. Gedney, “Finite difference, time-domain analysis of lossy transmission lines,” IEEE Trans. Electromag. Compat., Vol. 38, no. 1, pp. 15–24, Feb. 1996.
  • T.Sakurai, and A. R. Newton, “A simple MOSFET model for circuit analysis,” IEEE Trans. Electron Devices, Vol. 38, no. 4, pp. 887–94, Apr. 1991.
  • Tanner EDA tools. (2014). [Online]. Available: http://www.tannereda.com
  • F. Moll, and M. Roca, Interconnection Noise in VLSI Circuits, Dordrecht: Springer, 2004.
  • Narasimhan, M. Kasotiya, and R. Sridhar, “A low-swing differential signaling scheme for on-chip global interconnects,” in Proceeding of the IEEE Conference on Very Large Scale Integration Design, Kolkata, 2005, pp. 634–9.
  • P. V. Rao, and P. Mandal, “Current mode full duplex (CMFD) signaling for high speed chip to chip interconnect,” Microelectron. J., Vol. 42, no. 7, pp. 957–65, Jul. 2011.
  • N. M. Mahyuddin, G. Russell, and E. G. Chester, “Design and analysis of a low-swing driver scheme for long interconnects,” Microelectron. J., Vol. 42, no. 9, pp. 1039–48, Sep. 2011.
  • A. Mineyama, H. Ito, T. Ishii, K. Okada, and K. Masu, “LVDS-type on-chip transmission line interconnect with passive equalizers in 90 nm CMOS process,” in Proceeding of the IEEE Midwest Symposium Circuits Systems, Seoul, 2008, pp. 97–8.
  • A. P. Jose, G. Patounakis, and K. L. Shepard, “Pulsed current mode signaling for nearly speed of light intrachip communication,” IEEE J. Solid-State Circuits, Vol. 41, no. 4, pp. 772–80, Apr. 2006.
  • Semiconductor Industry Association, International Technology Roadmap for Semiconductors (ITRS). (2014). [Online]. Available: http://public.itrs.net
  • Predictive Technology Model (PTM). (2014). [Online]. Available: http://ptm.asu.edu
  • S. M. Kang, and Y. Leblebici, CMOS Digital Integrated Circuits, New Delhi: TMH, 2003.
  • I. Jiang, Y. W. Chang, and Y. Y. Jou, “Crosstalk driven interconnect optimization by simultaneous gate and wire sizing,” IEEE Trans. Comput.-Aided Des., Vol. 19, no. 9, pp. 999–1010, Nov. 2000.

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