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IETE Journal of Research Volume 17, 1971 - Issue 12
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Original Articles

Characterization of Planar Transistors Using Digital Computer

S. VenkateswaranDepartment of Electrical Engineering, Indian Institute of Technology, Kanpur
&
M. M. HasanDepartment of Electrical Engineering, Indian Institute of Technology, Kanpur
Pages 444-447 | Published online: 21 Aug 2015

References

  • Hoerni, J. A., “Planar silicon transistors and diodes”, IRE Electron Devices Meeting, Washington DC 1960.
  • Frosch, C. J. & Derrick, L., “Surface protection and selective masking during diffusion in silicon”, J. Electrochem. Sor., 104 (9) (1957), 547.
  • Fuller, C. S. & Ditzenberger, J. A., “Diffusion of donor and acceptor elements in silicon,” J. appl. Phys., 27 (5) (1956), 544.
  • Tannenbaum, E., “Detailed analysis of thin phosphorus diffused layers in p-type silicon”, Solid State Electronics, 2 (1) (1961), 123.
  • Atalla, M. M. & Tannenbaum, E., “Impurity redistribution and junction formation in silicon by thermal oxidation”, Bell syst. tech. J., 39 (4) (1960), 933.
  • Nicholas, K. H., “Studies of anomalous diffusion of impurities in silicon”, Solid State Electronics, 9 (1) (1966), 35.
  • Warner, R. M. (Jr), Integrated circuits—Design principles and fabrication (Motorola series), Ch. 3 (McGraw- Hill Book Co. Inc., New York), 1965.
  • Trumbore, F. A., “Solid solubilities of impurity elements in germanium and silicon”, Bell syst. tech. J. 39 (1) (1960), 205.
  • Grove, A. S., Physics and technology of semiconductor devices, Ch. 3 (John Wiley & Sons Inc., New York) 1967.
  • Kennedy, D. P & Murley, P. C., “Impurity atom distribution from a two-step diffusion process”, Proc IEEE, 52 (5) (1964), 620.
  • Ghosh, H. N., De La Moneda, F. H. & Dono, N. R., “Computer-aided transistor design, characterization and optimization”, Proc. IEEE, 55 (11) (1967), 1897.
  • Hasan, M. M. & Venkateswaran, S., “Cut-off frequency of a heterojunction transistor”, Int. J. Electronics 28 (5) (1970), 407.
  • Sze, S. M., Physics of semiconductor devices (John Wiley & Sons Inc., New York), 1969, 40.
  • Sze, S. M., Physics of semiconductor devices (John Wiley & Sons Inc., New York), 1969, 282.
  • Warner, R. M. (Jr), Integrated circuits—Design principles and fabrication (Motorola series) (McGraw-Hill Book Co. Inc., New York), 1965, 113.
  • Grove, A. S., Physics and technology of semiconductor devices (John Wiley & Sons Inc., New York), 1967, 165.
  • Lawrence, H. & Warner, R. M. (Jr), “Diffused junction depletion layer calculations”, Bell syst. tech. J., 39 (2) (1960), 389.

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