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IETE Journal of Research Volume 21, 1975 - Issue 2
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Original Articles

Fault Detection in a Two Level Negative Gate Network

A. PalIndian Telephone Industries, Naini, Allahabad.
,
A. PalitInstitute of Radio Physics and Electronics, University of Calcutta.
,
S. PalInstitute of Radio Physics and Electronics, University of Calcutta.
,
M. S. BasuIndian Telephone Industries, Naini, Allahabad.
&
A. K. ChoudhuryInstitute of Radio Physics and Electronics, University of Calcutta.
Pages 58-65 | Published online: 11 Jul 2015

REFERENCES

  • Penney (W M) and Lau (L). MOS Integrated Circuits and systems application of MOS LSI. Van Nostrand Reinhold Co. (1972).
  • Ibaraki (T) and Muroga (S). Synthesis of Networks with a minimum number of negative gates. IEEE Trans. Comput., C-20, (Jan. 1971); 49–58.
  • Sellers Jr. (F F), Hsiao (M Y) and Bearnson (L W). Analyzing Errors with Boolean difference. IEEE Trans. Comput., C-17, (July 1968), 676–683.
  • Akers (S B). A truth table method for the synthesis of Combinational logic. IRE trans. Comput., EC-10, (Dec. 1961); 604–615.
  • Ibaraki (T). Gate interconnection of switching networks using negative gates. IEEE trans. Comput., C-20, (June 1971), 698–706.
  • Yau, Stephen (S) and Tang, Yu-Shan. Algorithm for generating complete test sets for combinational logic circuits. IEEE, trans. Comput., C-20, No. 11, (Nov. 1971), 1245.
  • Kohavi, (ZV). Switching and finite automata theory. Mc-Graw-Hill Book Co., 1970.
  • Mc Cluskey JR., (EJ). Minimization of Boolean functions. Bell Systems Tech. J., 235, (Nov. 1956), 1417–1444.

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