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IETE Journal of Research Volume 27, 1981 - Issue 7
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Letters to the Editor

A Note on Negabinary Adder-Subtracter

G.S. RathDepartment of Electronics and Telecommunication Engineering, University, College of Engineering, Burla, Orissa768 018.
&
B. ChandramouliDepartment of Electronics Engineering, Madras Institute Technology Campus, Perarignar Anna University of Technology, Madras600 044.
Pages 256-257 | Received 12 Nov 1979, Published online: 11 Jul 2015

REFERENCES

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  • Zohar (S). c. Fast Hardware Fourier Transformation through Counting. IEEE Trans. C-22. 5: 1973: 433–441.
  • Agarwal (D P). a. Simultaneous Complex Search in Associative Memories. Comput. Systems Techl. Conf. London. 1977; 28–31, IEE Publ. No. 121. 1977; 180–184.
  • Agarwal (DP), b. Negabinary Complex Number Multiplier. Electronics Letters. 10. 1977; 502–503.
  • Pawlak (Z). An Electronic Digital Computer Based on the Base (—2) System. Bulletin de I Academic Polonaise des Sciences Series des Sciences Techniques. 7. 1955; 713–722.
  • Pawlak (Z). The Organisation of a Digital Computer Based on the (—2) Systems. Bull. Pol. Acad. Sci. 8. 1966; 253–258.
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  • Yuen (C K). A Note on Base (—2) Arithmetic Logic. IEEE Trans. C-24. 3: 1977; 325–329.
  • Rao (G S), Rao (M N) and Krishnamurthy (E V). Logical Design of a Negative Binary Adder-Subtracter. Int. J. Electron. 36, 1977; 537–542.
  • Langdon (CG). Subtraction b Minuend Complementation, IEEE Trans. C-18. 1969; 74–76.

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