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Original Articles

Computer Analysis of Cascaded Phase-Synchronized Oscillators

Pages 6-10 | Received 15 Apr 1985, Published online: 02 Jun 2015

REFERENCES

  • T. Shimamura & I. Eguchi, An analysis of jitter accumulation in a chain of PLL timing recovery circuits, IEEE Trans, vol COM-25, pp 1027–1032, Sep 1977.
  • G.B. Stracca & R. Cafissi, Systematic jitter in PAM digital transmission systems: engineering considerations for clock extractor design, Alta Frequenza, vol LII, pp 256–271, Apr 1983.
  • G.B. Stracca & C. Raelli, Comparison of tuned resonators and PLL's as timing extractors in long chains of regenerators, ibid, vol LII, pp 272–283, Apr 1983.
  • A. Del Pistoia, R. Giubilei & U. Mengali, Equivalent model of a clock recovery circuit, IEEE Trans, vol COM-31 pp 1187–1195, Oct 1983.
  • E. Lutz & K. Tröndle, Comparison between PLL's with integrating and non-integrating loop filters for timing recovery in repeater chains, Arch. Elektron. Übertragung, vol 35, pp 461–468, Dec 1981.
  • P. Hasan, Algorithm for solving a class of phase-lock loop equations, Electronics Letters, vol 19, pp 153–154, Mar 1983.

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