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Original Articles

Diagnostic Logic Graph for Testing MOS Circuits

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Pages 312-318 | Received 28 Apr 1986, Published online: 02 Jun 2015

REFERENCES

  • S K Jain & V D Agarwal, Modelling and test generation algorithms for MOS circuits, IEEE Trans on Comput, vol C-34, pp 426–433, May 1985.
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  • S M Reddy, M K Reddy & V D Agarwal, Robust test for stuck open faults in CMOS combinational logic circuits, Proc 14th Int Conf Faul-Tolerant Comput, Kissimmely FL, pp 44–49, June 1984.
  • S K Jain & V D Agarwal, Test generation for MOS circuits using D-algorithm, Proc 20th Design Automation Conf, Maimi Beach, FL, pp 64–70, June 1983.
  • A K Bose, P Kozak, C Y Lo, H N Nham, E Pacas-skewes & K Wu, A fault simulator for MOS LSI circuits, Proc 19 th Design Automation Conf, Las Vegas, NV, pp 400–409, June 1982.
  • K W Chiang & Z G Vranesic, Test generation for MOS complex gate networks, Proc 12 th Int Symp on Fault Tolerant Comput, Santa Monica, CA, pp 149–157, June 1982.
  • Y M El-Ziq & S Y H Su, Fault diagnostic of MOS combinational networks, IEEE Trans Comput, vol C-31, pp 129–139, Feb 1982.
  • K W Chiang & Z G Vranesic, Comments on fault diagnosis of MOS combinational networks, IEEE Trans Comput, vol C-33, pp 947, Oct 1984.
  • J S R Subrahmanyam, Diagnostic Logic Graph for Analysis & Diagnosis of Digital Networks, PhD Thesis, Dept of Computer Science & Engg, IIT, Kharagpur, Sept 1986.

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