MOS and Bipolar Memory Circuit Techniques

REFERENCES

• Special Issues on Logic and Memory, IEEE J Solid State Circuits, vol SC-14-SC-24, 1979–1989.
   Google Scholar
• H Taub & D Schilling, Digital Integrated Circuits, McGraw Hill, 1979.
   Google Scholar
• J Millman, Microelectronics, McGraw Hill, 1986.
   Google Scholar
• M I ElMasry (Ed), Digital MOS Circuits, IEEE Press, 1980.
   Google Scholar
• Bipolar and MOS Memory in Advanced Micro Devices Handbook, 1986.
   Google Scholar
• E Noguchi et al, LSI Memories, Fujitsu Scientific and Technical Journal, vol 121, pp 337–369 1985.
   Google Scholar
• L M Terman, MOSFET memory circuits, Proc IEEE, p 1044, July 1971.
   Google Scholar
• P K Chatterjee et al, A survey of high density dynamic RAM concepts, IEEE Trans Electron Devices, vol ED-26, p 827, June 1979.
   Web of Science ®Google Scholar
• V Leo-Rideout, One device cells for dynamic random access memory—A tutorial, IEEE Trans Electron Devices, vol ED-26, p 839, June 1979.
   Web of Science ®Google Scholar
• W M Penney & L Law, MOS integrated circuits, Van Nostrand, 1972.
   Google Scholar
• S M Sze, Physics of Semiconductor Devices, Wiley Eastern, 1981.
   Google Scholar
• S Muruga, VLSI Design.
   Google Scholar
• S K Wiedmann, Advancement in bipolar VLSI circuits and technology, IEEE J Solid State Circuit, vol SC-12, p 282, June 1984.
   Google Scholar
• J Lohstroh, The punchthrough device as a passive exponential load in fast static bipolar RAM cell, IEEE J Solid State Circuits, vol SC-14, p 840, Oct 1979.
   Web of Science ®Google Scholar
• R F Penoyer et al, An 18K bipolar dynamic random access memory, IEEE J Solid State Circuits, vol SC-19, p 861, Oct 1980.
   Google Scholar
• K Toyoda et al, A High speed 16 kbit ECL RAM, IEEE J Solid State Circuits, vol SC-18, p 509, Oct 83.
   Web of Science ®Google Scholar
• J Nokubo et al, A 4.5 ns access time, 1Kx4 bit ECL RAM, IEEE J Solid State Circuits, vol SC-18, p 515, Oct 1983.
   Web of Science ®Google Scholar
• C T Chuang, 1 ns, 5K bit ECL RAM, IEEE J Solid State Circuits, vol SC-21, p 670, Oct 1986.
   Web of Science ®Google Scholar
• N Homma et al, A 3.5 ns 2W 20 mm-2 16 kbit ECL bipolar RAM, IEEE J Solid State Circuits, vol SC-21, p 675, Oct 86.
   Web of Science ®Google Scholar
• K Ogiue et al, 13 ns, 500 mW, 66K bit ECL RAM with Hi-BiCMOS technology, IEEE J Solid State Circuits, vol SC-21, p 681, Oct 1986.
   Web of Science ®Google Scholar
• Tamba Nobuo et al, A 256K word x 1 bit ECL RAM with 8ns access time, IEEE J Solid State Circuits, vol SC-24, p 1021, Aug 89.
   Google Scholar
• T S Yang et al, A 4 ns 4K x l bit Two-port BiCMOS SRAM, IEEE J Solid State Circuits, vol SC-23, p 1030, Oct 88.
   Web of Science ®Google Scholar
• T Ohzone et al, 64 KB static random access memory, IEEE J Solid State Circuits, vol SC-15, p 236, 1980.
   Google Scholar
• K C Hardee & A R Sud, A fault tolerant 30 ns/375 mW, 16K x 1 nMOS static RAM, IEEE J Solid State Circuits, vol SC-16, p 438, Oct 1981.
   Google Scholar
• M Yoshimoto et al, Divided word line structure in the static RAM and its application to a 64K full CMOS RAM, IEEE J Solid State Circuits, vol SC-18, p 479, Oct 83.
   Web of Science ®Google Scholar
• L C Sood et al, A 35 ns, 2K x 8 HMOS static RAM, IEEE J Solid State Circuits, vol SC-18, p 498, Oct 1983.
   Web of Science ®Google Scholar
• T Yamanaka et al, A 25 ns 6K static RAM, IEEE J Solid State Circuits, vol SC-19, p 572, Oct 1984.
   Web of Science ®Google Scholar
• L F Childs & R T Hirose, An 18 ns CMOS SRAM, IEEE J Solid State Circuits, vol SC-19, p 545, Oct 1984.
   Web of Science ®Google Scholar
• S E Schuster et al, A 20 ns 64K nMOS RAM, IEEE J Solid State Circuits, vol SC-19, p 564, Oct 1984.
   Web of Science ®Google Scholar
• T Sakurai et al, A low power 46 ns, 256 Kbit CMOS static RAM with dynamic double word lines, IEEE J Solid State Circuits, vol SC-19, p 578, Oct 1984.
   Web of Science ®Google Scholar
• Y Kobayashi et al, A 10 μW standby power 256K CMOS SRAM, IEEE J Solid State Circuits, vol SC-20, p 935, Oct 1985.
   Web of Science ®Google Scholar
• S E Schuster et al, A 15-ns 64K RAM, IEEE J Solid State Circuit, vol SC-21, p 704, Oct 1986.
   Web of Science ®Google Scholar
• S Kayano et al, 25 ns 256K/64K x 4 CMOS SRAMs, IEEE J Solid State Circuits, vol SC-21, p 686, Oct 1986.
   Google Scholar
• F Miyaji et al, A 25 ns 4Mbit SRAM with dynamic bit line loads, IEEE J Solid State Circuits, vol SC-24, p 1213, Oct 1989.
   Web of Science ®Google Scholar
• K U Stein et al, Storage array and sense refresh circuit for single transistor memory cells, IEEE J Solid State Circuits, vol SC-7, p 336, Oct 1972.
   Web of Science ®Google Scholar
• K Fujishima et al, A 256K dynamic RAM with page-nibble mode, IEEE J Solid State Circuits, vol SC-18, p 470, Oct 1983.
   Web of Science ®Google Scholar
• F Baba et al, A 64K DRAM with 35 ns static column operation, IEEE J Solid State Circuits, vol SC-18, p 447, Oct 1983.
   Web of Science ®Google Scholar
• T Furuyama et al, An experimental 4 Mbit CMOS DRAM, IEEE J Solid State Circuits, vol SC-21, p 605, Oct 1986.
   Web of Science ®Google Scholar
• M Takada et al, 4 Mbits DRAM with half internal voltage bit line precharge, IEEE J Solid State Circuits, vol SC-21, p 612, Oct 1986.
   Web of Science ®Google Scholar
• A H Shah et al, 4 Mbit DRAM with trench transistor cell, IEEE J Solid State Circuits, vol SC-21, p 618, Oct 1986.
   Web of Science ®Google Scholar
• R C Foss & R Harland, Peripheral circuits for one transistor MOS SRAM, IEEE J Solid State Circuits, vol SC-10, p 255, Oct 1975.
   Web of Science ®Google Scholar
• S Fujii et al, A 45 ns 16 Mbit DRAM with triple well structure, IEEE J Solid State Circuits, vol SC-24, p 1170, Oct 1989.
   Web of Science ®Google Scholar
• K Arimoto et al, A 60 ns 3.5V only 16 Mbit DRAM with multipurpose register, ibid, p 1176.
   Google Scholar
• M Aoki et al, A 1.5 V DRAM for battery based applications, ibid, p 1206.
   Google Scholar
• T Watanabe et al, 1 Mbit BiCMOS vs CMOS DRAMS; Performance Comparison, IEEE J Solid State Circuits, vol SC-24, p 771, June 1989.
   Web of Science ®Google Scholar
• M W Knecht et al, A high speed ultra-low power 64K EPROM with on-chip test functions, IEEE J Solid State Circuits, vol SC-18, p 554, Oct 1983.
   Web of Science ®Google Scholar
• R Jolly et al, A 35 ns 64K EEPROM, IEEE J Solid State Circuits, vol SC-20, p 971, Oct 1985.
   Web of Science ®Google Scholar
• C S Bill et al, A temperature and process tolerant 64K EEPROM, IEEE J Solid State Circuits, vol SC-20, p 979, Oct 1985.
   Web of Science ®Google Scholar
• S Kohda et al, A giant chip multi gate transistor ROM circuit design, IEEE J Solid State Circuits, vol SC-21, p 713, Oct 1986.
   Web of Science ®Google Scholar
• M Momodomi et al, An experimental 4Mbit CMOS EEPROM with NAND structured cell, IEEE J Solid State Circuits, vol SC-24, p 1238, Oct 1989.
   Web of Science ®Google Scholar
• D Hoff et al, A 23 ns 256k EPROM with double layer metal and address transition detection, ibid, p 1250.
   Google Scholar
• V N Kynett et al, A 90 ns One-million erase-Program cycle 1 Mbit Flash Memory, ibid, p 1259.
   Google Scholar
• D J Lee et al, Control logic and cell design for a 4K NVRAM, IEEE J Solid State Circuits, vol SC-18, p 525, Oct 1983.
   Web of Science ®Google Scholar
• H McAdams et al, A 1 Mbit dynamic RAM with or test functions, IEEE J Solid State Circuits, vol SC-21, p 635, 1986.
   Web of Science ®Google Scholar
• LCMG Pfennings et al, A 14ns 256K x l CMOS SRAM with Multiple Test Modes, IEEE J Solid State Circuits, vol SC-24, p 874, Aug 1989.
   Web of Science ®Google Scholar
• S Murakami et al, Improvement of soft error rate in MOS SRAM, IEEE J Solid State Circuits, vol SC-24, p 869, Aug 1989.
   Web of Science ®Google Scholar
• M Hirayama et al, A GaAs 4 kbit SRAM with direct coupled FET logic, IEEE Solid State Circuits, vol SS-19, p 716, Oct 1984.
   Web of Science ®Google Scholar
• K Nishiuchi et al, A Sub-nanosecond HEMT 1 Kbit static RAM, IEEE J Solid State Circuits, vol SC-21, p 869, Oct 1986.
   Web of Science ®Google Scholar
• T Hayashi et al, Novel circuit technology for ECL-compatible GaAs static RAMs with small access time scattering, IEEE J Solid State Circuits, vol SC-22, p 853, Oct 1987.
   Web of Science ®Google Scholar
• R A Wood et al, An electrically alterable PLA for fast turnaround time VESI development hardware, IEEE J Solid State Circuits, vol SC-16, p 570, Oct 1981.
   Web of Science ®Google Scholar
• M Kokado et al, A 54K Gate ECL array with substrate power supply, IEEE J Solid State Circuits, vol SC-24, p 1271, Oct 1989.
   Web of Science ®Google Scholar
• M Okabe et al, A 400K Transistor CMOS SEA of gates array with continuous track allocations, IEEE J Solid State Circuits, vol SC-24, p 1280, Oct 1989.
   Web of Science ®Google Scholar
• H Satoh et al, A 209 K transistor ECL gate array with RAM, IEEE J Solid State Circuits, vol SC-24, p 1275, Oct 1989.
   Web of Science ®Google Scholar
• V G Pawar, Distributed arithmetic implementation of Transforms and simulation of memory and BiCMOS circuits, MTech Thesis, IIT Kharagpur, 1989.
   Google Scholar