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Original Articles

An Automated Channel Routing Technique for an IIL Gate Array

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Pages 282-286 | Published online: 02 Jun 2015

REFERENCES

  • T Nakamura et al, High-speed IIL circuits using a sidewall base contact strategy, IEEE Trans Electron Devices, vol ED-22, pp 248–252, Feb 1985.
  • J N Song & Y K Chen, Two-stage channel routing for CMOS gate arrays, IEEE Trans Computer-Aided Design, vol CAD-7, pp 439–450, April 1988.
  • A Bahraman et al, A versatile function generator chip imple mented in En IIL gate arrsy, IEEE J Solid State Circuits, vol SC-17, pp 671–676, Aug 1982.
  • E E Hollis, Design of VLSI Gate Array ICs, Prentice Hall, New Jersey, 1987, pp 118–148.
  • B Majumdar, K Ramoji Rao, S Rakshit, S Kai & S K Lahiri, An overview of bipolar gate arrays and a report of an IIL gate array design and development, Special Issue of IETE Technical Review on Semiconductor Industry (to be published).
  • R L Rivest & C M Fiduccia, A ‘Greedy’ channel router, Proc 19th Design Automation Conf, pp 418–424, 1982.

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