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Original Articles

A Test Pattern Generator for Sequential Circuits

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Pages 313-318 | Published online: 02 Jun 2015

REFERENCES

  • V D Agarwal & S C Seth, Tutorial: Test Generation for VLSI Chips, IEEE Computer Society, 1988.
  • W G Bouricius et al, Algorithms for detection of faults in logic circuits, IEEE Trans Computer, vol C-20, Nov 1971.
  • M A Breuer, A random and algorithmic technique for fault detection and test generation for sequentical circuits, IEEE Trans Computer, vol C-20, pp 1366–1370, Nov 1971.
  • H K Tony et al, Test generation sequential circuits, IEEE CAD, vol CAD-7, Oct 1988.
  • S M Reddy et al, A gate level model for CMOS combinational logic circuits with application to fault detection, Proc 21 st Design Automation Conf, pp 504–509, June 1984.
  • T W Williams et al, Design for testability—A survey, Proc IEEE, vol 71, pp 98–112, Jan 1983.

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