REFERENCES
- D K Jeong et al, Design of PLL based clock generation circuits, IEEE Journal of Solid State Circuits, vol SC-22, pp 255–261, April 1987.
- S Y Sun, An analog PLL based clock and data recovery circuit with high input jitter tolerance, JSSC, vol SC-24, pp 325–330, April 1989.
- R Woudsma & J M Noteboom, The modular design of clock-generator circuits in a CMOS building -block system, JSSC, vol SC-20, pp 770–774, June 1985.
- B Giebel et al. Digitally controlled oscillator, JSSC, vol SC-24, pp 640–645, June 1989.
- K M Ware et al, A 200 MHz CMOS phase locked loop with dual phase detectors, JSSC, vol 24, pp 1560–1568, Dec 1989.
- S M Walters & T Teoudet, Digital phase—locked loop with jitter bounded, IEEE Trans on Circuits and Systems, vol 36, pp 980–987, July 1989.
- M H Wakayama and A A Abidi, A 30-MHz low-jitter high-linearity CMOS voltage-controlled oscillator, JSSC, vol SC-21, pp 1074–1080, Dec 1987.
- M Banu, MOS oscillators with multi-decade tuning range and gigahertz maximum speed, JSSC, vol 23, pp 1386–1393, Dec 1988.
- M Soyuer & R G Meyer, High—frequency phase—locked loops in monolithic bipolar technology, JSSC, vol 24, pp 787–795, June 1989.
- F M Gardner, Charge-pump phase-lock loops, IEEE Trans Comm, vol Com 28, pp 1849–1858, Nov 1980.
- IC manual, Signetics, 1986.
- R Yeager, Loop gain compensation in phase locked loop, RCA Rev, vol 47, pp 78–87, March 1986.