REFERENCES
- Yamanaka et al, Torus: Terabit per second ATM switching system architecture based on distributed internal speedup ATM switch, IEEE Jr on SAC. vol 15, no 5, p 807, June 1997.
- Caglayan et al, Design and performance evaluation of a Banyan network based interconnection structure for ATM switches, IEEE Jr on SAC, vol 15, no 5, p 708. June 1997.
- Hashemi et al, The single queue switch: A building block for switches with programmable scheduling, IEEE Jr on SAC, vol 15, no 5, p 785, June 1997.
- Rathgeb et al, The mainstreet xpress core services node -A versatile ATM switch architecture for the full service network, IEEE Jr on SAC, vol 15, no 5, p 795, June 1997.
- E W Zegura & A Pattavina, Architectures for ATM switching system, IEEE Comm Mag, pp 28–48, Feb 1993.
- Madihally J Narasimha, The Batcher Banyan self-routing network: Universality and simplification, IEEE Trans on Comm, vol 36. no 10, pp 1175–1178, Oct 1988.
- H Ahmadi & W E Denzel A survey of modern high performance switching Techniques, IEEE Jr on SAC, vol 7. no 7, pp 1091–1103, Sep 1989.
- L R Goke & G J Lipovski, Banyan networks for partitioning microprocessor systems, in Proc of 1st Annu Int Symp Comput Architecture, pp 21–28, December 1973.
- KE Batcher Sorting networks and their applications, Proc spring joint computer conf AFIPS 1968, pp 307–314, 1968.
- D M Dias & J R Jump, Analysis and simulation of buffered delta networks, IEEE Trans Comput, vol C-30, pp 273–282, April 1981.
- J S Turner, New Directions in communication (or which way to the information age?). IEEE Commun Mag, vol 24, pp 8–15, October 1986.
- S Shanmugavel, J Bhavani & J Raja, Performance of Input buffered sort banyan ATM Switching network, Proc of INFOCOMTECH 2000 held at Jodhpur, India during March 23–24, 1998.
- J Raja & S Shanmugavel, Sorter based Inter-stage buffered ATM switch Network, Proc of NCC '99, pp 609–613. held at IIT, Kharagpur, India during Jan 29–31, 1999.
- J Raja & S Shanmugavel, Performance analysis of Shared output buffered sort banyan ATM switch network. Proc of NCC 2000, pp 118–121 held at IIT, New Delhi, India during Jan 28–30, 2000.
- H Oliata & T Kitama, A cell loss recovery method using FEC in ATM networks, IEEE Jr on SAC, vol 9. no 9, pp 1471–1483, 1991.
- E W Biersack, Performance evaluation of FEC in an ATM environment, IEEE Jr on SAC, vol II, no 4, pp 631–639, 1993.
- W Leand, M Tappu, W Willinger & D Wilson, On the self similar nature of Ethernet traffic (Extended Version), IEEE ACM Transactions on networking, 2(1), pp 1–15, February 1994.
- V Paxson, Fast, Approximate synthesis of Fractional Gaussian Noise for generating Self-Similar Network Traffic, Computer Communication review, 27(5), pp 5–18, October, 1997.