A Subthreshold Surface Potential and Drain Current Model for Lateral Asymmetric Channel (LAC) MOSFETs

REFERENCES

• S Odanaka & A Hiroki, Potential design and transport property of 0.1 - μm MOSFET with asymmetric channel profile, IEEE Trans Electron Devices, vol 44, no 4, pp 595–600, April 1997.
   Web of Science ®Google Scholar
• V R Rao, W Hansch & I Eisele, Simulation, fabrication and characterization of high performance planar-doped- barrier sub 100 nm channel MOSFETs, In IEDM Tech Dig, 1997, pp 811–814.
   Google Scholar
• J P John, V Ilderem, C Park, J Teplik, K Klein & S Cheng, A low voltage graded-channel MOSFET (LV-GCMOS) for sub 1-volt microcontroller applications, In VLSI Tech Dig, 1996, pp 178–179.
   Google Scholar
• B Cheng, V R Rao & J C S Woo, Exploration of velocity overshoot in a high-performance deep sub-0.1—μm SOI MOSFET with asymmetric channel profile, IEEE Electron Device Letter, vol 20, no 10, pp 538–540, October 1999.
   Web of Science ®Google Scholar
• B Cheng, A Inani, R Rao & J C S Woo, Channel engineering for high speed sub-1.0 V power supply deep sub-micron CMOS, In VLSI Tech Dig, 1999, pp 69–70.
   Google Scholar
• A Chatterjee, K Vasanth, D T Grider, M Nandakumar, G Pollack, R Aggarwal, M Rodder & H Shichijo, Transistor design issues in integrated analog functions with high performance digital CMOS, In VLSI Tech Dig, 1999, pp 147–148.
   Google Scholar
• H V Deshpande, B Cheng & J C S Woo, Channel engineering for analog device design in deep submicron CMOS technology for system on chip applications, IEEE Trans Electron Devices, vol 49, no 9, pp 1558–1565, September 2002.
   Web of Science ®Google Scholar
• K Narasimhulu, D K Sharma & V R Rao, Impact of lateral asymmetric channel doping on deep submicrometer mixed-signal device and circuit performance, IEEE Trans. Electron Devices, vol 50. no 12, pp 2481–2489, December 2003.
   Web of Science ®Google Scholar
• K Narasimhulu, M P Desai, S G Narendra & V R Rao, The effect of LAC doping on deep submicrometer transistor capacitances and its influence on device RF performance, IEEE Trans Electron Devices, vol 51, no 9, pp 1416–1423, September 2004.
   Web of Science ®Google Scholar
• H Shin & S Lee, An 0.1 -μm asymmetric halo by large- angle-tilt implant (AHLATI) MOSFET for high performance and reliability, IEEE Trans Electron Devices, vol 45, no 4, pp. 820–822, April 1999.
   Google Scholar
• E Vittoz & J Fellrath, CMOS analog integrated circuits based on weak inversion operation, IEEE J Solid-State Circuits, vol SC-12, no 3, pp 224–231, June 1977.
   Web of Science ®Google Scholar
• B C Paul, A Raychowdhury & K Roy, Device optimization for digital subthreshold logic operation, IEEE Trans Electron Devices, vol 52, no 2, pp 237–247, February 2005.
   Web of Science ®Google Scholar
• R M Swanson & J D Meindl, Ion-implanted complementary MOS transistors in low-voltage circuits, IEEE J Solid-State Circuits, vol SC-7, no 2, pp 146–153, April 1972.
   Web of Science ®Google Scholar
• T A Fjeldly & M Shur, Threshold voltage modeling and the subthreshold regime of operation of short-channel MOSFET's, IEEE Trans Electron Devices, vol 40, no 1, pp 137–145, January 1993.
   Web of Science ®Google Scholar
• S Baishya, A Mallik & C K Sarkar, A subthreshold surface potential model for short-channel MOSFET taking into account the varying depth of channel depletion layer due to source and drain junctions, IEEE Trans Electron Devices, vol 53, no 3, pp 507–514, March 2006.
   Web of Science ®Google Scholar
• YS Pang & J R Brews, Analytical subthreshold surface potential model for pocket n-MOSFETs, IEEE Trans Electron Devices, vol 49, no 12, pp 2209–2216, December 2002.
   Web of Science ®Google Scholar
• Y Tour & T H Ning, Fundamentals of Modern VLSI Devices, Cambridge Univ Press, Cambridge, 1998.
   Google Scholar
• Y Tsividis, Operation and Modeling of the MOS Transistor, 2nd ed., Mcgraw-Hill, New York, 1999.
   Google Scholar
• C S Ho, J J Liou, K-Y Huang & C -C Cheng, An analytical subthreshold current model for pocket-implanted NMOSFETs, IEEE Trans Electron Devices, vol 50, no 6, pp 1475–1479, June 2003.
   Web of Science ®Google Scholar
• B Yu, C H J Wann, E D Nowak, K Noda & C Hu, Short-channel effect improved by lateral channel-engineering in deep-submicronmeter MOSFET's, IEEE Trans Electron Devices, vol 44, no 4, pp 627–634, April 1997.
   Web of Science ®Google Scholar
• Z-H Liu, C Hu, J -H Huang, T -Y Chan, M -C Jeng, P K Ko & Y C Cheng, Threshold voltage model for deep-submicrometer MOSFET's, IEEE Trans Electron Devices, vol 40, no 1, pp 86–95, January 1993.
   Web of Science ®Google Scholar
• H Shin, G M Yeric, A F Tasch & C M Maziar, Physically-based models for effective mobility and local-field mobility of electrons in MOS inversion layers, Solid-State Electron, vol 34, no 6, pp 545–552, 1991.
   Web of Science ®Google Scholar
• International Technology Roadmap for Semiconductors, and 1999 and 2001 (ed).
   Google Scholar