References
- S. Busqests-Monge, J. D. Ortego, J. Bordonau, J. A. Beristain, and J. Rocabert, “Closed loop control of a three phase neutral point clamped inverter using an optimized virtual vector based pulse width modulation,” IEEE Trans. Ind. Electron., Vol. 55, no. 5, pp. 2061–9, May 2008.
- J.-J. Park, T.-J. Kim, and D.-S. Hyun, “Study of neutral point variation for three level NPC inverter under fault condition,” IEEE Trans. Power Electron., pp. 983–8, May 2008.
- M. El Gamal, A. Lotfy, and G. E. M. Ali, “Firing approach for higher levels of diode clamped multilevel inverters,” in Proceedings of International Middle East Power Systems Conference, Egypt, Dec. 2010, pp. 50–4.
- J. Holtz, and N. Oikonomou, “Neutral point potential balancing algorithm at low modulation index for three level inverter medium voltage drives,” IEEE Trans. Ind. Appl., Vol. 43, no. 3, pp. 761–8, May/Jun. 2007.
- A. Bendre, G. Venkataramanan, D. Rosene, and V. Srinivasan, “Modeling and design of a neutral point voltage regulator for a three level diode clamped inverter using multiple carrier modulation,” IEEE Trans. Ind. Electron., Vol. 53, no. 3, pp. 718–26, Jun. 2006.
- S. Mekhilef, H. I. Khudhur, and H. Belkamel, “DC link capacitor voltage balancing in three level neutral point clamped inverter,” in Proceedings of IEEE COMPEL Conference, Malaysia, pp. 1–4, Jun. 2012.
- Y. He, J. Liu, J. Tang, Z. Wang, and Y. Zou, “Theoretical analysis and control of DC neutral-point voltage balance of three level inverters in active power filters,” J Power Electron., Vol. 12, no. 2, pp. 344–56, Mar. 2012.
- C. Wang, and Y. Li, “Analysis and calculation of zero-sequence voltage considering neutral-point potential balancing in three-level NPC converters,” IEEE Trans. Ind. Electron., Vol. 57, no. 7, pp. 2262–71, Jul. 2010.
- W. Yao, H. Hu, and Z. Lu, “Comparisons of space vector modulation and carrier based modulation of multilevel inverters,” IEEE Trans. Power Electron., Vol. 23, no. 1, pp. 45–51, Jan. 2008.
- D.-W. Kang, Y.-H. Lee, B.-S. Suh, et al., “An improved carrier-based SVPWM method using leg voltage redundancies in generalized cascaded multilevel inverter topology,” IEEE Trans. Power Electron., Vol. 18, no. 1, pp. 180–87, Jan. 2003.
- O. Lopez, J. Alvarez, J. Doval-Gandoy, F. D. Freijdo, et al., “Comparison of the FPGA implementation of two multilevel space vector PWM algorithms,” IEEE Trans. Ind. Electron., Vol. 55, no. 4, pp. 1537–47, Apr. 2008.
- H. Hu, W. Yao, and Z. Lu, “Design and implementation of three level space vector PWM IP core for FPGAs,” IEEE Trans. Power Electron., Vol. 22, no. 6, pp. 2234–44, Nov. 2007.
- Z. Shu, J. Tang, Y. Guo, and J. Lian, “An efficient SVPWM algorithm with low computational overhead for three-phase inverters,” IEEE Trans. Power Electron., Vol. 22, no. 5, pp. 1797–805, Sep. 2007.
- S. Nageswari, and V. S. Kumar, “FPGA implementation of sampled space vector pulse width modulation technique for two level inverter,” J Electr. Eng., Vol. 12, no. 1, pp. 182–7, Mar. 2012.
- W.-S. Oh, S.-K. Han, S.-W. Choi, and G.-W. Moon, “Three phase three level PWM switched voltage source inverter with zero neutral point potential,” IEEE Trans. Power Electron., Vol. 21, no. 5, pp. 1320–7, Sep. 2006.
- D.-W. Chung, J.-S. Kim, and S.-K. Sul, “Unified voltage modulation technique for real time three phase power conversion,” IEEE Trans. Ind. Appl., Vol. 34, no. 2, pp. 374–80, Mar./Apr. 1998.