REFERENCES
- P. Andreani, and H. Sjoland, “Noise optimisation of an inductively degenerated CMOS low noise amplifier,” IEEE Trans. Circuits Syst., Vol. 48, pp. 834–42, Sep. 2001.
- T. H. Jin, and T. W. Kim, “A 5.5-mW +9.4dBm IIP3 1.8 dB NF CMOS LNA employing multiple gated transistors with capacitance desensitization,” IEEE Trans. Microw. Theory Tech., Vol. 58, pp. 2529–37, Oct. 2010.
- R. Bhattacharya, R. Gupta, A. Basu, and S. K. Koul, “Analysis and design of a fully integrated, linear dual band LNA for WLAN and Wi-MAX applications,” in Proceedings of the IEEE Asia Pacific Microwave Conference (APMC), Kaoshiung, Taiwan, Dec. 2012, pp. 759–61.
- T. H. Jin, and T. W. Kim, “A 6.75 mW 12.45 dBm IIP3 1.76 dB NF 0.9 GHz CMOS LNA employing multiple gated transistors with bulk-bias control,” IEEE Microw. Wirel. Comp. Lett., Vol 21, pp. 616–8, Nov. 2011.
- J. Lee, J. Lee, B. Kim, B. E. Kim, and C. Nguyen, “A highly linear low-noise amplifier using a wideband linearization technique with tunable multiple gated transistors,” in Proceeddings of the IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Seattle, WA, Jun. 2013, pp. 181–4.
- Y. M. Kim, H. Han, and T. W. Kim, “A 0.6-V +4 dBm IIP3 LC folded cascode CMOS LNA with gm linearization,” IEEE Trans. Circuits Syst., Vol. 60, pp. 122–6, Mar. 2013.
- S. Hu, W. Li, Y. Huang, and Z. Hong, “A high-linearity receiver RF front-end with a high-performance 25%-duty-cycle LO generator for WCDMA/GSM applications,” in Proceedings of the IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), Beijing, China, Dec. 2011, pp. 161–4.
- P. Wambacq, Distortion Analysis of Analog ICs. Dordrecht, the Netherlands: Kluwer Academic Press, 2001.
- D. Shaeffer, and T. Lee, “A 1.5V, 1.5 GHz CMOS low noise amplifier,” IEEE J. Solid-State Circuits, Vol. 32, pp. 745–59, May 1997.
- L. Belostotski, and J. W. Haslett, “Noise figure optimization of inductively degenerated CMOS LNAs with integrated gate inductors,” IEEE Trans. Circuits Syst., Vol. 53, pp 1409–22, Jul. 2006.