References
- V. Papaefstathiou, and I. Papaefstathiou, “A memory efficient, 100 Gb/sec MAC classification engine,” in IEEE Conference on Local Computer Networks, Sydney, Australia, 2005, pp. 470–471.
- H. Altunbasak, and H. Owen, “An architectural framework for data link layer security with security interlayering,” in Proceedings of the IEEE SoutheastCon, Richmond, VA, 2007, pp. 607–614.
- H. Reynolds, and D. Marschke, JUNOS Enterprise Switching, 1st ed. Sebastopol, CA: O’Reilly, 2009.
- Y. Bhaiji, Layer 2 Attacks & Mitigation Techniques. San Jose, CA: Cisco Systems, 2005.
- A. Chakrabarti, and G. Manimaran, “Internet infrastructure security: A taxonomy,” IEEE Netw., Vol. 16, no. 6, pp. 13–21, Nov./Dec. 2002.
- S. R. Ramlee, “Content addressable memory (CAM) in layer 2 switching,” presented at the IT Security for the Next Generation, Asia Pacific & MEA Cup, Hong Kong, Mar. 14–16, 2012.
- A. Mason, CCNP Security Secure 642-637 Quick Reference: Cisco Layer 2 Security. Indianapolis, IN: Cisco Press, 2011.
- MAC Address Table Commands, Allied Telesis. (2015, March, 29). Available: http://alliedtelesis.com/manuals/DC2552WEBUGRevA/MAC_address_reference.html.
- N. R. Indukuri, “Layer 2 security for Smart Grid networks,” in IEEE International Conference on Advanced Networks and Telecommuncations Systems, Bangalore, 2012, pp. 99–104.
- K. H. Yeung, D. Fung, and K. Y. Wong, “Tools for attacking layer 2 network infrastructure,” in Proceedings of the International MultiConference of Engineers and Computer Scientists 2008 Vol. II, Hong Kong, 2008, pp. 19–21.
- R. Schlenk, “Flooding traffic reduction through optimized address learning in carrier-grade ethernet networks,” in ITG Symposium on Photonic Networks, Leipzig, 2008, pp. 1–7.
- D. Davis, Lock down Cisco switch port security. (2015, March, 31). Available: http://www.techrepublic.com/blog/it-security/lock-down-cisco-switch-port-security-88196.
- K. Pagiamtzis, and A. Sheikholeslami, “Content-addressable memory (CAM) circuits and architectures: A tutorial and survey,” IEEE J. Solid-State Circuits, Vol. 41, no. 3, pp. 712–27, Mar. 2006.