130
Views
3
CrossRef citations to date
0
Altmetric
Articles

Exploring the Asymmetric Characteristics of a Double Gate MOSFET with Linearly Graded Binary Metal Alloy Gate Electrode for Enhanced Performance

, &

REFERENCES

  • E. Weste, Principles of CMOS VLSI Design: A System Perspective. Upper Saddle River, NJ: Pearson Education, 2003, ch. 2.
  • M. I. Current, S. W. Bedell, I. J. Malik, L. M. Feng, and F. J. Henley, “What is the future of sub-100 nm CMOS: Ultra shallow junctions or ultrathin SOI?” Solid State Technol., vol. 43, pp. 66–77, Sep. 2000.
  • F. Balestra, M. Benachir, J. Brini, and G. Ghibaudo, “Analytical models of subthreshold swing and threshold voltage for thin- and ultrathin-film SOI MOSFETs,” IEEE Trans. Electron Devices, vol. 37, pp. 2303–2311, Nov. 1990.
  • Y. Taur, “Analytical solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs,” IEEE Trans. Electron Devices, vol. 48(12), pp. 2861–2869, Dec. 2001.
  • S. Spedo and C. Fiegna, “Comparison of and asymmetric double-gate MOSFETs-tunneling currents and hot electrons,” in Proceedings of the IEEE Semiconductor Device Research Symposium, Washington DC, 2002, pp. 601–604.
  • T. Ghani, K. Mistry, P. Packam, S. Thompson, M. Stettler, S. Tyagi, and M. Bohr, “Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors,” in Symposium on VLSI Technical Digest, Honolulu, HI, 2000, pp. 174–175.
  • X. Tang, V. K. De, and J. D. Meindl, “Intrinsic MOSFET parameter fluctuations due to random dopant placement,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 5(4), pp. 369–376, Dec. 1997.
  • A. Tsormpatzoglou, C. A. Dimitriadis, R. Clerc, G. Pananakakis, and G. Ghibaudo, “Threshold voltage model for short-channel undoped symmetrical double-gate MOSFETs,” IEEE Trans. Electron Devices, vol. 55(9), pp. 2512–2516, Sep. 2008.
  • T. Poiroux, O. Rozeau, S. Martinie, P. Scheer, S. Puget, M. A. Jaud, S. E. Ghouli, J. C. Barbé, A. Juge, and O. Faynot, “UTSOI2: A complete physical compact model for UTBB and independent double gate MOSFETs,” in Proceedings of the IEEE International Electron Devices Meeting (IEDM), Washington, DC, 2013, pp. 12.4.1–12.4.48.
  • N. Sharan and S. Mahapatra, “A short-channel common double-gate MOSFET model adapted to gate oxide thickness asymmetry,” IEEE Trans. Electron Devices, vol. 61(8), pp. 2732–2737, Aug. 2014.
  • S. Jandhyala, R. Kashyap, C. Anghel, and S. Mahapatra, “A simple charge model for symmetric double-gate MOSFETs adapted to gateoxide-thickness asymmetry,” IEEE Trans. Electron Devices, vol. 59(4), pp. 1002–1007, Apr. 2012.
  • N. Sharan and S. Mahapatra, “Nonquasi-static charge model for common double-gate MOSFETs adapted to gate oxide thickness asymmetry,” IEEE Trans. Electron Devices, vol. 60(7), pp. 2419–2422, Jul. 2013.
  • K. Kim and J. G. Fossum, “Double-gate CMOS: Symmetrical- versus asymmetrical-gate devices,” IEEE Trans. Electron Devices, vol. 48(2), pp. 294–299, Feb. 2001.
  • K. Papathanasiou, C. G. Theodorou, A. Tsormpatzoglou, D. H. Tassis, C. A. Dimitriadis, M. Bucher, and G. Ghibaudo, “Symmetrical unified compact model of short-channel double-gate MOSFETs,” Solid-State Electron., vol. 69, pp. 55–61, Mar. 2012.
  • Bing-Yue Tsui and Chih-Feng Huang, “Wide range work function modulation of binary alloys for MOSFET application,” IEEE Electron Device Lett., vol. 24(3), pp. 153–155, Mar. 2003.
  • B. Manna, S. Sarkhel, N. Islam, S. Sarkar, and S. K. Sarkar, “Spatial composition grading of binary metal alloy gate electrode for short-channel SOI/SON MOSFET application,” IEEE Trans. Electron Devices, vol. 59(12), pp. 3280–3287, Dec. 2012.
  • S. Sarkhel and S. K. Sarkar, “A compact quasi 3D threshold voltage modeling and performance analysis of a novel linearly graded binary metal alloy quadruple gate MOSFET for subdued short channel effects,” Superlattices Microstruct., vol. 82, pp. 293–302, Jun. 2015.
  • S. Sarkhel and S. K. Sarkar, “A comprehensive two dimensional analytical study of a nanoscale linearly graded binary metal alloy gate cylindrical junctionless MOSFET for improved short channel performance,” J. Comput. Electron., vol. 13(4), pp. 925–932, Dec. 2014.
  • R. Ishii, K. Matsumura, A. Sakai, and T. Sakata, “Work function of binary alloys,” Appl. Surf. Sci., vol. 169–170, pp. 658–661, Jan. 2001.
  • C. D. Gelatt and H. Ehrenreich, “Charge transfer in alloys: AgAu,” Phys. Rev. B, vol. 10(2), pp. 398–415, Jul. 1974.
  • A. Pan, R. Liu, M. Sun, and C.-Z. Ning, “Spatial composition grading of quaternary ZnCdSSe alloy nanowires with tunable light emission between 350 and 710 nm on a single substrate,” ACS Nano, vol. 4(2), pp. 671–680, Jan. 2010.
  • I. Ohkubo, H. M. Christen, P. Khalifah, S. Sathyamurthy, H. Y. Zhai, C. M. Rouleau, D. G. Mandrus, and D. H. Lowndes, “Continuous composition-spread thin films of transition metal oxides by pulsed-laser deposition,” Appl. Surf. Sci., vol. 223, pp. 35–38, Feb. 2004.
  • H. M. Christen, C. M. Rouleau, I. Ohkubo, H. Y. Zhai, H. N. Lee, S. Sathyamurthy, and D. H. Lowndes, “An improved continuous compositional-spread technique based on pulsed-laser deposition and applicable to large substrate areas,” Rev. Sci. Instrum., vol. 74, pp. 4058–4062, Sep. 2003.
  • A. Tsormpatzoglou, C. A. Dimitriadis, R. Clerc, G. Pananakakis, and G. Ghibaudo, “Semianalytical modeling of short-channel effects in lightly doped silicon trigate MOSFETs,” IEEE Trans. Electron Devices, vol. 55(10), pp. 2623–2631, Oct. 2008.
  • K. K. Young, “Short-channel effects in fully depleted SOI MOSFET's,” IEEE Trans. Electron Devices, vol. 36, pp. 399–402, Feb. 1989.
  • N. Fasarakis, T. Karatsori, D. H. Tassis, C. G. Theodorou, F. Andrieu, O. Faynot, G. Ghibaudo, and C. A. Dimitriadis, “Analytical modeling of threshold voltage and interface ideality factor of nanoscale ultrathin body and buried oxide SOI MOSFETs with back gate control,” IEEE Trans. Electron Devices, vol. 61(4), pp. 969–975, Apr. 2014.
  • S. Deb, N. B. Singh, D. Das, A. K. De, and S. K. Sarkar, “Analytical I-V model of SOI and SON MOSFETs: A comparative analysis,” Int. J. Electron., vol. 98(11), pp. 1465–1481, Nov. 2011,.
  • M. Fei, L. H. Xia, K. Q. Wei, and F. Ji-Bin, “A threshold voltage analytical model for high-k gate dielectric MOSFETs with fully overlapped lightly doped drain structures,” Chin. Phys. B, vol. 21(5), pp. 057304–1–057304-6, May 2012.

Reprints and Corporate Permissions

Please note: Selecting permissions does not provide access to the full text of the article, please see our help page How do I view content?

To request a reprint or corporate permissions for this article, please click on the relevant link below:

Academic Permissions

Please note: Selecting permissions does not provide access to the full text of the article, please see our help page How do I view content?

Obtain permissions instantly via Rightslink by clicking on the button below:

If you are unable to obtain permissions via Rightslink, please complete and submit this Permissions form. For more information, please visit our Permissions help page.