Variability Analysis of Stochastic Parameters on the Electrical Performance of On-Chip Current-Mode Interconnect System

REFERENCES

• Semiconductor Industry Association, International Technology Roadmap for Semiconductors (ITRS). Available: http://public.itrs.net, 2012.
   Google Scholar
• O. S. Unsal, J. W. Tschanz, K. Bowman, V. De, X. Vera, A. Gonzlez, and O. Ergin, “Impact of parameter variations on circuits and microarchitecture,” IEEE Micro, Vol. 26, no. 6, pp. 30–9, 2006.
   Web of Science ®Google Scholar
• E. Salman and E. G. Friedman, High Performance Integrated circuit Design. New York: McGraw-Hill, 2012.
   Google Scholar
• R. Dhiman and R. Chandel, Compact Models and Performance Investigations for Sub-Threshold Interconnects. New Delhi: Springer, 2014.
   Google Scholar
• B. Zhai, S. Hanson, D. Blaauw, and D. Sylvester, “A variation-tolerant sub-200 mV 6-T subthreshold SRAM,” IEEE J. Solid-State Circuits, Vol. 43, no. 10, pp. 2338–48, 2008.
   Web of Science ®Google Scholar
• F. Boeuf, M. Sellier, A. Farcy, and T. Skotnicki, “An evaluation of the CMOS technology roadmap from the point of view of variability, interconnects, and power dissipation,” IEEE Trans. Electron Devices, Vol. 55, no. 6, pp. 1433–40, 2008.
   Web of Science ®Google Scholar
• A. K. Wong, R. A. Ferguson, and S. M. Mansfield, “The mask error factor in optical lithography,” IEEE Trans. Semiconduct. Manuf., Vol. 13, no. 2, pp. 235–42, 2000.
   Web of Science ®Google Scholar
• T. A. Brunner, “Impact of lens aberrations on optical lithography,” IBM J. Res. Dev., Vol. 41, no. 1.2, pp. 57–67, 1997.
   Web of Science ®Google Scholar
• P. Stolk, F. P. Widdershoven, and D. M. Klaassen, “Modeling statistical dopant fluctuations in MOS transistors,” IEEE Trans. Electron Devices, Vol. 45, no. 9, pp. 1960–71, 1998.
   Web of Science ®Google Scholar
• M. K. Majumder, J. Kumar, and B. K. Kaushik, “Process-induced delay variation in SWCNT, MWCNT, and mixed CNT interconnects,” IETE J. Res., Vol. 61, no. 5, pp. 533–40, 2015.
   Web of Science ®Google Scholar
• M. Shoaran, A. Tajalli, M. Alioto, A. Schmid, and Y. Leblebici, “Analysis and characterization of variability in subthreshold source coupled logic circuits,” IEEE Trans. Circuits Syst, Vol. 62, no. 2, pp. 458–67, 2015.
   Google Scholar
• L. Jianwei, D. Gang, Y. Yintang, and W. Zeng, “Fast statistical delay evaluation of RC interconnect in the presence of process variations,” J. Semiconduct., Vol. 31, no. 4, pp. 1–5, 2010.
   Google Scholar
• R. Chandel, S. Sarkar, and R. P. Agarwal, “Performance controlling parameters of voltage-scaled repeaters for long interconnects,” IETE J. Res., Vol. 51, no. 2, pp. 107–13, 2005.
   Web of Science ®Google Scholar
• T. D. Drysdale, A. R. Brown, G. Roy, S. Roy, and A. Asenov, “Capacitance variability of short range interconnects,” J. Comput. Electron, Vol. 7, no. 3, pp. 124–7, 2007.
   Web of Science ®Google Scholar
• V. Venkatraman and W. Burleson, “Robust multi-level current-mode on-chip interconnect signaling in the presence of process variations,” in Proceedings of IEEE Quality of Electronic Design Symposium, 2005, pp. 522–7.
   Google Scholar
• A. P. Jose, G. Patounakis, and L. K. Shepard, “Pulsed current-mode signaling for nearly speed-of-light intrachip communication,” IEEE J. Solid-State Circuits, Vol. 41, no. 4, pp. 772–80, 2006.
   Web of Science ®Google Scholar
• F. Yuan, CMOS Current Mode Circuits for Data Communication. New York: Springer, 2007.
   Google Scholar
• M. Dave, M. Jain, M. S. Baghini, and D. Sharma, “A variation tolerant current mode signaling scheme for on-chip interconnects,” IEEE Trans. Very Large Scale Integr. Syst., Vol. 21, no. 2, pp. 342–53, 2013.
   Web of Science ®Google Scholar
• Y. Agrawal, R. Chandel, and R. Dhiman, “High performance current mode receiver design for on-chip VLSI interconnects,” Springer Proc. Int. Conf. ICA Series: Adv. Intell. Syst. Comput., Vol. 343, pp. 527–36, Feb. 2015, ch. 54.
   Google Scholar
• R. Bashirullah, “Reduced delay sensitivity to process induced variability in current mode sensing interconnects,” Electron. Lett., Vol. 42, no. 9, pp. 531–2, 2006.
   Web of Science ®Google Scholar
• S. Tuuna, E. Nigussie, J. Isoaho, and H. Tenhunen, “Modeling of energy dissipation in RLC current-mode signaling,” IEEE Trans. Very Large Scale Integr. Syst., Vol. 20, no. 6, pp. 1146–51, May 2012.
   Web of Science ®Google Scholar
• Y. Agrawal, R. Chandel, and R. Dhiman, “Design and analysis of efficient multilevel receiver for current mode interconnect system,” in Proc. IEEE SCEECS, 2014, pp. 1–6.
   Google Scholar
• R. Bashirullah, W. Liu, and R. K. Cavin, “Current-mode signaling in deep submicrometer global interconnects,” IEEE Trans. Very Large Scale Integr. Syst., Vol. 11, no. 3, pp. 406–17, Jun. 2003.
   Web of Science ®Google Scholar
• K. Lee, M. Qazi, J. Kong, and A. P. Chandrakasan, “Low-swing signaling on monolithically integrated global graphene interconnects,” IEEE Trans. Electron Devices, Vol. 57, no. 12, pp. 3418–25, Dec. 2010.
   Web of Science ®Google Scholar
• Predictive technology models. Available: http://ptm.asu.edu, 2015.
   Google Scholar
• Tanner EDA tools for SPICE simulation. Available: http://www.tannereda.com, 2015.
   Google Scholar
• S. M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits. New Delhi: TMH, 2003.
   Google Scholar
• V. Siddhartha and A. K. Singh, “Mechanical and dry sliding wear characterization of short glass fiber reinforced polyester-based homogeneous and their functionality graded composite materials,” in Proc. IMechE, Part L: J. Mater. Des. Appl., Vol. 229, no. 4, pp. 274–298, 2013.
   Google Scholar
• C. T. Su and C. J. Yeh, “Optimization of the Cu wire bonding process for IC assembly using Taguchi methods,” Microlectron. Reliability, Vol. 51, no. 1, 2011.
   Google Scholar
• A. R. A. Arkadan, N. A. Arwar, and A. O. Hariri, “EM-Taguchi module for characterization of WAD,” IEEE Trans. Magn, Vol. 51, no. 3, 2015.
   Web of Science ®Google Scholar
• Minitab tool. Available: http://www.minitab.com, 2015.
   Google Scholar
• E. Nigussie, S. Tunna, J. Plosila, and J. Isoaho, “Analysis of crosstalk and process variations effects on on-chip interconnects,” in IEEE Symposium on Sytsem-on-Chip, Tampere, Nov. 2006, pp. 1–4.
   Google Scholar
• V. Mehrota, “Modeling the effects of systematic process variation on circuit performance,” Ph.D. thesis, Dept. Elect. Comput. Eng., Massachusetts Institute of Technology, Cambridge, MA, 2001.
   Google Scholar
• K. Narasimha, M. K. Majumder, and B. K. Kaushik, “Delay uncertainty in MLGNR interconnects under process induced variations of width, doping, dielectric thickness and mean free path,” J. Comput. Electron., Vol. 13, no. 3, pp. 639–46, Sep. 2014.
   Web of Science ®Google Scholar
• Y. Agrawal and R. Chandel, “Crosstalk analysis of current-mode signalling-coupled RLC interconnects using FDTD technique,” IETE Tech. Rev., Vol. 33. no. 2, pp. 148–59, 2016.
   Web of Science ®Google Scholar
• M. Sahoo, P. Ghosal, and H. Rahaman, “Modeling and analysis of crosstalk induced effects in multiwalled carbon nanotube interconnects: An ABCD parameter based approach,” IEEE Trans. Nanotechnol., Vol. 14, no. 2, pp. 259–74, Mar. 2015.
   Web of Science ®Google Scholar
• W. S. Zhao and W. Y. Yin, “Comparative study on multilayer graphene nanoribbon (MLGNR) interconnects,” IEEE Trans. Electromagn. Compat., Vol. 56, no. 3, pp. 638–45, Jun. 2014.
   Web of Science ®Google Scholar
• V. R. Kumar, B. K. Kaushik, and A. Patnaik, “An accurate FDTD model for crosstalk analysis of CMOS-gate-driven coupled RLC interconnects,” IEEE Trans. Electromagn. Compat., Vol. 56, no. 5, pp. 1185–93, Sep. 2014.
   Web of Science ®Google Scholar