A 2D Potential Based Threshold Voltage Model Analysis and Comparison of Junctionless Symmetric Double Gate Vertical Slit Field Effect Transistor

REFERENCES

• J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yann, I. Ferain, P. Razavi, B. O. Neill, A. Blake, M. White, A. M. Kelleher, B. McCarthy, and R. Murphy, “Nanowire transistors without junctions,” Nat. Nanotechnol., vol. ED-5, pp. 225–229, Mar. 2010.
   Web of Science ®Google Scholar
• B. Ghosh, P. Bal, and M. Partha, “A junctionless tunnel field effect transistor with low subthreshold slope,” J. Comput. Electron., vol. ED-12, pp. 428–436, Mar. 2013.
   Web of Science ®Google Scholar
• C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, and J. P. Colinge, “Junctionless multigate field-effect transistor,” Appl. Phys. Lett., vol. ED-94, pp. 053511–1–053511–2, Feb. 2009.
   Web of Science ®Google Scholar
• A. Pfitzner, “Vertical-slit field effect transistor (VeSFET) – design space exploration and DC model,” in Proceedings of the International Conference Mixed Design of Integrated Circuits and Systems, Gliwice, Poland, 2011, pp. 151–156.
   Google Scholar
• W. Maly, A. Pfitzner, N. Singh, D. Kasporwicz, M. Marek-sadowska, Y.-W. Lin, Z. Chen, N. Shen, and X. Li, “Dual gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration,” Tecreport no. CSSI 08–02, USA, 2008.
   Google Scholar
• Y.-W. Lin, M. Marek-Sadowska, W. Maly, A. Pfitzner, and D. Kasporwicz, “Is there always performance overhead for regular fabric?,” Int. Conf. Comput. Des., pp. 557–562, Jan. 2008.
   Google Scholar
• W. Maly, “Integrated circuits fabrication and associated methods devices and systems,” U.S. Non-Provisional Patent Application serial Number CMU Docket 06-091; DMC Docket 06-001PCTCMU, Sep. 04, 2012.
   Google Scholar
• A. Kamath, Z. Chen, N. Shen, N. Singh, G. Q. Lo, D-Lee Kwong, D. Kasprowicz, A. Pfitzner, and W. Maly, “Realising AND and OR functions with single vertical-slit field effect transistor,” IEEE Electron Dev. Lett., vol. ED-33, pp. 152–154, Feb. 2012.
   Web of Science ®Google Scholar
• L. Barbut, F. Jazaeri, D. Bouvet, and J. M. Sallese, “Downscaling and short channel effects in twin gate junctionless vertical slit FETs,” Int. J. Microelectron. Comp. Sci., vol. ED-4, pp. 103–109, Oct. 2013.
   Google Scholar
• G. Zhang, Z. Shao, and K. Zhou, “Threshold voltage model of short channel FD-SOI MOSFET with vertical Gaussian profile,” IEEE Trans. Electron Devices, vol. ED-55, pp. 803–809, Mar. 2008.
   Web of Science ®Google Scholar
• V. S. Nandakumar and M. Marek- Sadoswska, “A Low energy network on chip fabric for 3-D multi-core architecture,” IEEE J. Emerging Sel. Top. Circuits Syst., vol. ED-2, pp. 266–277, Jun. 2012.
   Web of Science ®Google Scholar
• J. E. Lilienfield, “Method and apparatus for controlling electric current,” U.S. Patent 1 745 175, Jan. 28, 1930.
   Google Scholar
• W. Maly, N. Singh, Z. Chen, N. Shen, X. Li, A. Pfitzner, D. Kasprowicz, W. Kuzmicz, Y-W Lin and, and M. Marek- Sadowska, “Twin gate vertical slit FET (VeSFET) for highly periodic layout and 3D integration,” in Proceedings of the International Conference Mixed Design of Integrated Circuits and Systems, Gliwice, Poland, 2011, pp. 145–150.
   Google Scholar
• A. Pfitzner and D. Kasprowicz, “Compact model of vertical slit field effect transistor (VeSFET),” in Proceedings of the European Solid State Circuit Conference, Gliwice, 2011.
   Google Scholar
• A. Kamath, Z. Chen, N. Shen, X. Li, N. Singh, G.-Q. Lo, D.-L. Kwong, D. Kasporwicz, A. Pfitzner, and W. Maly, “Logic functionality in vertical slit field effect transistor,” in Proceedings of the International Conference on Solid-state and Integrated Circuit, Singapore, pp. 1–4, 2012.
   Google Scholar
• T.-K. Chiang, “A quasi-two-dimensional threshold voltage model for short-channel junctionless double gate-MOSFETs,” IEEE Trans. Electron Devices, vol. ED-59, pp. 2284–2289, Aug. 2012.
   Web of Science ®Google Scholar
• Y. Omura, S. Horiguchi, M. Tabe, and K. Kishi, “Quantum-mechanical effects on the threshold voltage of ultrathin-SOI nMOSFETs,” IEEE Electron Dev. Lett., vol. ED-14, pp. 569–571, Dec. 1993.
   Web of Science ®Google Scholar
• T. Chaudhary and G. Khanna, “Analytical modeling of drain current and short channel effects of junctionless double gate vertical slit field effect transistor,” J. Nanoelectron. Optoelectron., vol. ED-11, pp. 1–7, Oct. 2016.
   Web of Science ®Google Scholar
• J. M. Sallese, N. Chevillon, F. Pregaldiny, C. Lallement, and B. Iniguez, “The equivalent-thickness concept for doped symmetric DG MOSFETs,” IEEE Trans. Electron Devices, vol. ED-57, pp. 2917–2924, Nov. 2010.
   Web of Science ®Google Scholar
• J. M. Sallese, N. Chevillon, F. Pregaldiny, C. Lallement, and B. Iniguez, “Charge based modeling of junctionless double gate field effect transistors,” IEEE Trans. Electron Devices, vol. ED-58, pp. 2628–2637, Aug. 2011.
   Web of Science ®Google Scholar
• C. Li, Y. Zhuang, S. Di, and R. Han, “Subthreshold behavior models for nanoscale short – channel junctionless cylindrical surrounding gate MOSFETs,” IEEE Trans. Electron Devices, vol. ED-60, pp. 3655–3662, Nov. 2013.
   Web of Science ®Google Scholar
• F. Jazaeri, L. Barbut, A. Koukab, and J.-M. Sallese, “Analytical model for ultra-thin body junctionless symmetric double gate MOSFETs in subthreshold regime,” Solid-State Electron., vol. ED-82, pp. 103–110, Feb. 2013.
   Web of Science ®Google Scholar
• L. Barbut, F. Jazaeri, D. Bouvet, and J. M. Sallese, “Design space of twin gate junctionless vertical slit field effect transistors,” in Proceedings of the International Conference on Mixed Design of Integrated Circuits and Systems, Gdynia, Poland, 2013, pp. 393–396.
   Google Scholar
• K. Sazuki and S. Pidin, “Short channel single gate SOI MOSFET model,” IEEE Trans. Electron Devices, vol. ED-50, pp. 1297–1305, May 2003.
   Web of Science ®Google Scholar
• “Sentaurus structure editor user's manual,” Synopsys Int.
   Google Scholar
• “Sentaurus Inspect User's Manual,” Synopsys Int.
   Google Scholar
• C. W. Lee, I. Ferain, A. Afjalian, R. Yan, N. D. Akhavan, P. Razavi, and J. P. Colinge, “Performance estimation of junctionless multigate transistors,” Solid State Electron., vol. ED-54, pp. 97–103, Feb. 2010.
   Web of Science ®Google Scholar