Design of a new CMOS Low-Power Analogue Neuron

REFERENCES

• M. Dolatshahi and N. Dorosti. “Design of a low-power CMOS analog neural network,” in Proc. of ISCSE 2011, Izmir, 2011, pp. 465–471.
   Google Scholar
• N. Chasta, S. Chouhan and Y. Kumar. (2012). “Analog VLSI implementation of neural network architecture for signal processing,” Int. J. VLSI Des. Commun. Sys. (VLSICS) 3 (2), pp. 243–259.
   Google Scholar
• G. Samtas. (2014). “Measurement and evaluation of surface roughness based on optic system using image processing and artificial neural network,” Int. J. Adv. Manuf. Technol. 73 (1), pp. 353–364.
   Web of Science ®Google Scholar
• L. Gatet, H. Tap-Béteille, M. Lescure. (2008). “Analog neural network implementation for a real-time surface classification application,” IEEE Sensors J. 8 (8), pp. 1413–1421.
   Web of Science ®Google Scholar
• L. I. Perlovsky and R. W. Deming. (2007). “Neural networks for improved tracking,” IEEE Trans. Neural Netw. 18 (6), pp. 1854–1857.
   Google Scholar
• H. Widyantara, M. Rivai and D. Purwanto. (2012). “Neural network for electronic nose using field programmable analog array,” Int. J. Electr. Comp. Eng.(IJECE) 2 (6), pp. 739–747.
   Google Scholar
• Ch.Heng Pan, H.Yi Hsieh and K. Tiong Tang. (2013). “An analog multilayer perceptron neural network for a portable electronic nose,” Sensors 13, pp. 193–207.
   Web of Science ®Google Scholar
• S. L. Phung and A. Bouzerdoum. (2007). “A pyramidal neural network for visual pattern recognition,” IEEE Trans. Neural Netw. 18 (2), pp. 329–343.
   PubMedGoogle Scholar
• J. K. Basu, D. Bhattacharyya and T. H. Kim. (2010). “Use of artificial neural network in pattern recognition,” Int. J.Software Eng. Appl. 4 (2), pp. 23–34.
   Google Scholar
• K. Gorynski, I. Safian and W. Gradzki. (2014). “Artificial neural networks approach to early lung cancer detection,” Central Eur. J. Med. 9 (5), pp. 632–641.
   Google Scholar
• R. Dlugosz, T. Talaska, and W. Pedrycz. (2011). “Current-mode analog adaptive mechanism for ultra-low-power neural networks,” IEEE Trans. Circuits Syst. II 58 (1), pp. 31–35.
   Google Scholar
• D. J. Jwo, (2005). “GPS navigation solutions by analogue neural etwork least-squares processors,” J. Navig. 58 (1), pp. 105–118.
   Web of Science ®Google Scholar
• J. S. Wang, and Y. P. Chen. (2006). “A fully automated recurrent neural network for unknown dynamic system identification and control,” IEEE Trans. Circuits Syst. I 53 (6), pp. 1363–1372.
   Google Scholar
• G. Cauwenberghs. (1996). “An analog VLSI recurrent neural network learning a continuous-time trajectory,” IEEE Trans. Neural Netw. 7 (2), pp. 346–361.
   PubMedGoogle Scholar
• A. Wang, B. H. Calhoun and A. P. Chandrakasan, “Sub-threshold Design for Ultra Low-Power Systems”, in Series on Integrated Circuits and Systems. New York, NY: Springer, 2007.
   Google Scholar
• H. Li, D. Zhang and S. Foo. (2006). “A stochastic digital implementation of a neural network controller for small wind turbine systems,” IEEE Trans. Power Electron. 21 (5), pp. 1502–1507.
   Web of Science ®Google Scholar
• Z. Nagy and P. Szolgay. (2003). “Configureurable multilayer CNN-UM emulator on FPGA,” IEEE Trans. Circuits Syst. I 50 (6), pp. 774–778.
   Google Scholar
• R. Wojtyna and T. Talaska. (2006). “Transresistance CMOS neuron for adaptive neural networks implemented in hardware,” Bull. Polish Acad. Sci. 54 (4), pp. 443–448.
   Google Scholar
• S. Azizian, K. Fathi, B. Mashoufi and F. Derogarian, “Implementation of a programmable neuron in 0.35 μm CMOS process for multi-layer ANN application,” in Proc. Int. Conf. Comp. Tool (EUROCON), Lisbon, Portugal, 2011, pp. 27–29.
   Google Scholar
• G. Han and E. Sanchez-Sinencio. (1998). “CMOS transconductance multiplier a tutorial,” IEEE Trans. Circuits Syst. II 45 (12), pp. 1550–1563.
   Google Scholar
• S. Yuwono, Ch. Jeong, S. Han and S. Lee, “Current-reused single-ended current-output multiplier as a core circuit in a UWB pulse detector,” in 13th International Conference on Advanced Communication Technology (ICACT), Seoul, South Korea, 2011, pp. 902–905.
   Google Scholar
• G. Khodabandehloo, M. Mirhassani and M. Ahmadi. (2012). “Analog implementation of a novel resistive-type sigmoidal neuron,” IEEE Trans. VLSI Syst. 20 (4), pp. 750–754.
   Web of Science ®Google Scholar
• M. Carrasco Robles and L. Serrano. (2009), “A novel minimum- size activation function and its derivative,” IEEE Trans. Circuits Syst. II 56 (4), pp. 280–284.
   Google Scholar
• L. Gatet, H. Tap-Béteille and F. Bony (2009). “Comparison between analog and digital neural network implementations for range-finding applications,” IEEE Trans. Neural Netw. 20 (3), pp. 460–470.
   PubMed Web of Science ®Google Scholar