Optimization Approaches for Core Mapping on Networks on Chip

REFERENCES

• R. Marculescu , U. Y. Ogras , L. Peh , and N. E. Jerger , “Outstanding research problems in NoC design: System, microarchitecture, and circuit perspectives,” IEEE Trans. Comput. Des. Integr. Circuits Syst. , Vol. 28, no. 1, pp. 3–21, Jan. 2009.
   Web of Science ®Google Scholar
• L. Benini and G. De Micheli , “Networks on chips: a new SoC paradigm,” Computer , Vol. 35, no. 1, pp. 70–78, Jan. 2002.
   Web of Science ®Google Scholar
• N. Jafarzadeh , M. Palesi , A. Khademzadeh , and A. Afzali-Kusha , “Data encoding techniques for reducing energy consumption in network-on-chip,” IEEE Trans. Very Large Scale Integr. Syst., Vol. 22, no. 3, pp. 675–685, Mar. 2014.
   Web of Science ®Google Scholar
• S. Niroomand , S. Takács , and B. Vizvári , “To lay out or not to lay out?,” Ann. Oper. Res. , Vol. 191, no. 1, pp. 183–192, Nov. 2011.
   Web of Science ®Google Scholar
• W. Chaovalitwongse , P. M. Pardalos , and O. A. Prokopyev , “A new linearization technique for multi-quadratic 0-1 programming problems,” Oper. Res. Lett. , Vol. 32, no. 6, pp. 517–522, Nov. 2004.
   Web of Science ®Google Scholar
• O. He , S. Dong , W. Jang , J. Bian , and D. Z. Pan , “UNISM: Unified scheduling and mapping for general networks on chip,” IEEE Trans. Very Large Scale Integr. Syst. , Vol. 20, no. 8, pp. 1496–1509, Aug. 2012.
   Web of Science ®Google Scholar
• A. Mahmoodi-Rad , S. Molla-Alizadeh-Zavardehi , R. Dehghan , M. Sanei , and S. Niroomand , “Genetic and differential evolution algorithms for the allocation of customers to potential distribution centers in a fuzzy environment,” Int. J. Adv. Manuf. Technol. , Vol. 70, no. 9–12, pp. 1939–1954, Feb. 2014.
   Web of Science ®Google Scholar
• S. Niroomand and B. Vizvari , “Exact mathematical formulations and metaheuristic algorithms for production cost minimization: a case study of the cable industry,” Int. Trans. Oper. Res. , Vol. 22, no. 3, pp. 519–544, May 2015.
   Web of Science ®Google Scholar
• M. Hajiaghaei-Keshteli , S. M. Sajadifar , and R. Haji , “Determination of the economical policy of a three-echelon inventory system with (R, Q) ordering policy and information sharing,” Int. J. Adv. Manuf. Technol., Vol. 55, no. 5–8, pp. 831–841, Jul. 2011.
   Web of Science ®Google Scholar
• M. Hajiaghaei-Keshteli and M. Aminnayeri , “Solving the integrated scheduling of production and rail transportation problem by Keshtel algorithm,” Appl. Soft Comput. , Vol. 25, pp. 184–203, Dec. 2014.
   Web of Science ®Google Scholar
• K. Srinivasan , K. S. Chatha , and G. Konjevod , “Linear-programming-based techniques for synthesis of network-on-chip architectures,” IEEE Trans. Very Large Scale Integr. Syst., Vol. 14, no. 4, pp. 407–420, Apr. 2006.
   Web of Science ®Google Scholar
• S. Murali and G. De Micheli , “Bandwidth-constrained mapping of cores onto NoC architectures,” Des. Autom. Test Eur., Date, pp. 896–901, Feb. 2004.
   Google Scholar
• J. Hu and R. Marculescu , “Energy- and performance-aware mapping for regular NoC architectures,” IEEE Trans. Comput. Des. Integr. Circuits Syst. , Vol. 24, no. 4, pp. 551–562, Apr. 2005.
   Web of Science ®Google Scholar
• J. Hu and R. Marculescu , “Energy-aware mapping for tile-based NoC architectures under performance constraints,” ASP-DAC , pp. 233–239, Jan. 2003.
   Google Scholar
• D. Bertozzi , A. Jalabert , S. Murali , and S. Member , “NoC synthesis flow for customized domain specific multiprocessor systems-on-chip,” IEEE Trans. Parallel Distrib. Syst. , Vol. 16, no. 2, pp. 113–129, Feb. 2005.
   Web of Science ®Google Scholar
• G. Leary , K. Srinivasan , K. Mehta , and K. S. Chatha , “Design of network-on-chip architectures with a genetic algorithm-based technique,” IEEE Trans. Very Large Scale Integr. Syst. , Vol. 17, no. 5, pp. 674–687, May 2009.
   Web of Science ®Google Scholar
• K. S. Chatha , K. Srinivasan , and G. Konjevod , “Automated techniques for synthesis of application-specific network-on-chip architectures,” IEEE Trans. Comput. Des. Integr. Circuits Syst. , Vol. 27, no. 8, pp. 1425–1438, Aug. 2008.
   Web of Science ®Google Scholar
• S. Murali , M. Coenen , A. Radulescu , K. Goossens , and G. De Micheli , “A methodology for mapping multiple use-cases onto networks on chips,” Des. Autom. Test Eur., Date, Vol. 1, pp. 1–6, Mar. 2006.
   Google Scholar
• J. Hu and R. Marculescu , “Exploiting the routing flexibility for energy/performance-aware mapping of regular NoC architectures,” Des. Autom. Test Eur., Date , pp. 688–693, Dec. 2003.
   Google Scholar
• K. Srinivasan and K. S. Chatha , “A technique for low energy mapping and routing in network-on-chip architectures,” ISLPED ’05 , pp. 387–392, Aug. 2005.
   Google Scholar
• P. K. Sahu , T. Shah , K. Manna , and S. Chattopadhyay , “Application mapping onto mesh-based network-on-chip using discrete particle swarm optimization,” IEEE Trans. Very Large Scale Integr. Syst. , Vol. 22, no. 2, pp. 300–312, Feb. 2014.
   Web of Science ®Google Scholar
• A. F. Alkaya and E. Duman , “Combining and solving sequence dependent traveling salesman and quadratic assignment problems in PCB assembly,” Discret. Appl. Math. , Vol. 192, no. 2015, pp. 2–16, Sep. 2015.
   Web of Science ®Google Scholar
• M. Laurent and M. Seminaroti , “The quadratic assignment problem is easy for Robinsonian matrices with Toeplitz structure,” Oper. Res. Lett. , Vol. 43, no. 1, pp. 103–109, Jan. 2015.
   Web of Science ®Google Scholar
• B. Rostami and F. Malucelli , “A revised reformulation-linearization technique for the quadratic assignment problem,” Discret. Optim. , Vol. 14, pp. 97–103, Nov. 2014.
   Web of Science ®Google Scholar
• W. Adams and L. Waddell , “Linear programming insights into solvable cases of the quadratic assignment problem,” Discret. Optim. , Vol. 14, pp. 46–60, Nov. 2014.
   Web of Science ®Google Scholar
• S. Kirkpatrick , C. D. Gelatt Jr. , M. P. Vecchi , “Optimization by Simulated Annealing,” Science , Vol. 220, no. 4598, pp. 671–680, May 1983.
   PubMed Web of Science ®Google Scholar
• A. Baykasoğlu and N. N. Z. Gindy , “A simulated annealing algorithm for dynamic layout problem,” Comput. Oper. Res. , Vol. 28, no. 14, pp. 1403–1426, Dec. 2001.
   Web of Science ®Google Scholar
• R. Şahin , K. Ertoral , and O. Türkbey , “A simulated annealing heuristic for the dynamic layout problem with budget constraint,” Comput. Ind. Eng. , Vol. 59, no. 2, pp. 308–313, Sep. 2010.
   Web of Science ®Google Scholar
• S. Niroomand , A. Hadi-Vencheh , R. Şahin , and B. Vizvari , “Modified migrating birds optimization algorithm for closed loop layout with exact distances in flexible manufacturing systems,” Expert Syst. Appl. , Vol. 42, pp. 6586–6597, Nov. 2015.
   Web of Science ®Google Scholar
• S. S. Heragu and Attahiru Sule Alfa , “Experimental analysis of simulated annealing based algorithms for the layout problem,” Eur. J. Oper. Res. , Vol. 57, no. 2, pp. 190–202, Mar. 1992.
   Web of Science ®Google Scholar
• M. Braglia , “Optimisation of a simulated-annealing-based heuristic for single row machine layout problem by genetic algorithm,” Int. Trans. Oper. Res. , Vol. 3, no. 1, pp. 37–49, Jan. 1996.
   Google Scholar
• M. Gen , R. Cheng , Genetic Algorithms and Engineering Design . New York : Wiley, 1997.
   Google Scholar
• M. Gen , R. Cheng , Genetic Algorithms and Engineering Optimization . New York : Wiley, 2000.
   Google Scholar
• M. Hajiaghaei-Keshteli , “The allocation of customers to potential distribution centers in supply chain networks: GA and AIA approaches,” Appl. Soft Comput. J. , Vol. 11, no. 2, pp. 2069–2078, Mar. 2011.
   Web of Science ®Google Scholar
• S. Molla-Alizadeh-Zavardehi , M. Hajiaghaei-Keshteli , and R. Tavakkoli-Moghaddam , “Solving a capacitated fixed-charge transportation problem by artificial immune and genetic algorithms with a Prufer number representation,” Expert Syst. Appl. , Vol. 38, no. 8, pp. 10462–10474, Aug. 2011.
   Web of Science ®Google Scholar
• M. R. Delavar , M. Hajiaghaei-Keshteli , and S. Molla-Alizadeh-Zavardehi , “Genetic algorithms for coordinated scheduling of production and air transportation,” Expert Syst. Appl. , Vol. 37, no. 12, pp. 8255–8266, Dec. 2010.
   Web of Science ®Google Scholar
• Y. Zhang , C. Liu , S. Wei , C. Wei , and F. Liu , “ECG quality assessment based on a kernel support vector machine and genetic algorithm with a feature matrix,” Frontiers of Inform. Tech. Electronic Eng. , Vol. 15, no. 7, pp. 564–573, Jul. 2014.
   Google Scholar
• L. Zhang , M. Lampe , and Z. Wang , “A hybrid genetic algorithm to optimize device allocation in industrial Ethernet networks with real-time constraints,” Frontiers of Inform. Tech. Electronic Eng. , Vol. 12, no. 12, pp. 965–975, Dec. 2011.
   Google Scholar
• L. Garcia-Hernandez , H. Pierreval , L. Salas-Morera , and a. Arauzo-Azofra , “Handling qualitative aspects in unequal area facility layout problem: An interactive genetic algorithm,” Appl. Soft Comput. J. , Vol. 13, no. 4, pp. 1718–1727, Apr. 2013.
   Web of Science ®Google Scholar
• A. Eiben and J. Smith , Introduction to Evolutionary Computing . Heidelberg: Springer-Verlag, 2003.
   Google Scholar
• G. Paul , “Comparative performance of tabu search and simulated annealing heuristics for the quadratic assignment problem,” Oper. Res. Lett. , Vol. 38, no. 6, pp. 577–581, Nov. 2010.
   Web of Science ®Google Scholar
• G. Paul , “An efficient implementation of the robust tabu search heuristic for sparse quadratic assignment problems,” Eur. J. Oper. Res. , Vol. 209, no. 3, pp. 215–218, Mar. 2011.
   Web of Science ®Google Scholar
• M. Czapiński , “An effective parallel multistart tabu search for quadratic assignment problem on CUDA platform,” J. Parallel Distrib. Comput. , Vol. 73, no. 11, pp. 1461–1468, Nov. 2013.
   Web of Science ®Google Scholar
• X. He , A. Chen , W. Chaovalitwongse , and H. X. Liu , “An improved linearization technique for a class of quadratic 0-1 programming problems,” Optim. Lett. , Vol. 6, no. 1, pp. 31–41, Jan. 2012.
   Web of Science ®Google Scholar
• International Technology Roadmap for Semiconductors (ITRS), http://www.itrs.net, 2010.
   Google Scholar